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NXP Semiconductors MCF5253 Reference Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. MCF5253 Reference Manual,
  25. about this book
  26. revision history
  27. register summary
  28. MCF5253 Overview
  29. MCF5253 Block Diagram
  30. MCF5253 Feature Details
  31. MCF5253 Functional Overview
  32. Instruction Cache
  33. ATA Controller
  34. CD-ROM Encoder/Decoder
  35. Timer Module
  36. GPIO Interface
  37. Sleep and Wake-Up Modes
  38. Overview
  39. GPIO
  40. Read-Write Control
  41. Chip Selects
  42. Serial Module Signals
  43. Digital Audio Interface Signals
  44. Subcode Interface
  45. Queued Serial Peripheral Interface (QSPI)
  46. USB Controller
  47. Test Mode
  48. BDM/JTAG Signals
  49. On-Chip Linear Regulator
  50. Processor Pipelines
  51. ColdFire Processor Memory Map and Register Definitions
  52. Address Registers (A0–A6)
  53. Description
  54. Supervisor Memory Map and Register Description
  55. Vector Base Register (VBR)
  56. Exception Stack Frame Definition
  57. Processor Exceptions
  58. Address Error Exception
  59. Debug Interrupt
  60. Fault-on-Fault Halt
  61. MOVE Instruction Execution Times
  62. Standard One Operand Instruction Execution Times
  63. Miscellaneous Instruction Execution Times
  64. Branch Instruction Execution Times
  65. PLL Features
  66. PLL Memory Map and Register Definitions
  67. PLL Operation
  68. Dynamic Clock Switching
  69. Reduced Power Mode
  70. Enter Sleep Mode
  71. Instruction Cache Features
  72. Instruction Cache Physical Organization
  73. Memory Reference Attributes
  74. Instruction Cache Memory Map and Register Definitions
  75. Instruction Cache Register
  76. Access Control Registers
  77. SRAM Features
  78. SRAM Initialization
  79. SDRAM Features
  80. Synchronous Operation
  81. DRAM Controller Signals in Synchronous Mode
  82. DRAM Controller Registers
  83. DRAM Address and Control (DACR0) (Synchronous Mode)
  84. DRAM Controller Mask Registers (DMR0)
  85. General Synchronous Operation Guidelines
  86. Interfacing Example
  87. Continuous Page Mode
  88. Auto-Refresh Operation
  89. Self-Refresh Operation
  90. Initialization Sequence
  91. SDRAM Example
  92. SDRAM Interface Configuration
  93. DACR Initialization
  94. DMR Initialization
  95. Mode Register Initialization
  96. Initialization Code
  97. Bus Features
  98. Address Bus
  99. Reset In
  100. Bus Cycle Execution
  101. Read Cycle
  102. Write Cycle
  103. Back-to-Back Bus Cycles
  104. Burst Cycles
  105. Misaligned Operands
  106. Reset Operation
  107. Software Watchdog Reset
  108. SIM Overview
  109. SIM Register Memory Map
  110. SIM Module Programming Registers
  111. Device ID Register
  112. Primary Interrupt Controller Registers
  113. Interrupt Mask Register
  114. Secondary Interrupt Controller Registers
  115. Interrupt Level Selection
  116. Spurious Vector Register
  117. Software Interrupts
  118. System Protection and Reset Status Registers
  119. System Protection Control Register
  120. Software Watchdog Interrupt Vector Register
  121. Software Watchdog Service Register
  122. Internal Arbitration Operation
  123. PARK Register Bit Configuration
  124. General Purpose I/Os
  125. General Purpose Inputs
  126. General Purpose Input Interrupts
  127. General Purpose Outputs
  128. Multiplexed Pin Configuration
  129. Chip Select Features
  130. CS1/QSPI_CS3/GPIO28
  131. Chip Select Operation
  132. Global Chip-Select Operation
  133. Chip Select Module Registers
  134. Chip Select Mask Register
  135. Chip Select Control Register
  136. Code Example
  137. Timer Module Overview
  138. Timer Signal Output
  139. Configuring the Timer for Output Mode (TIMER0)
  140. Timer Reference Registers (TRR0, TRR1)
  141. Timer Counters (TCN0, TCN1)
  142. Timer Initialization Example Code
  143. ADC Memory Map and Register Definitions
  144. AD Value Register (ADvalue)
  145. Functional Description
  146. IDE and SmartMedia Overview
  147. Buffer Enables BUFENB1, BUFENB2, and Associated Logic
  148. Generation of IDE_DIOR and IDE_DIOW
  149. Cycle Termination on CS2 (IDE_DIOR, IDE_DIOW)
  150. SmartMedia Interface Setup
  151. SmartMedia Timing
  152. Setting Up The IDE Interface
  153. IDE Timing Diagram
  154. Flash Media Interface
  155. Flash Media Interface Memory Map and Register Definitions
  156. Flash Media Interface Operation
  157. Flash Media Command Registers in Memory Stick Mode
  158. Flash Media Command Register 2 in Secure Digital Mode
  159. Flash Media Data Registers
  160. Flash Media Status Register
  161. Flash Media Interface Operation in Memory Stick Mode
  162. Reading Data from the Memory Stick
  163. Writing Data to the Memory Stick
  164. Interrupt from Memory Stick
  165. Send Command to Card
  166. Write Data to Card
  167. Commonly Used Commands in SD Mode
  168. Send Command to Card (Receive Multiple Data Blocks and Status)
  169. Send Command to Card (Write Multiple Data Blocks)
  170. DMA Features
  171. DMA Request
  172. DMA Module Overview
  173. DMA Memory Map and Register Definitions
  174. Source Address Register
  175. Destination Address Register
  176. Byte Count Register
  177. DMA Control Register
  178. DMA Status Register
  179. DMA Interrupt Vector Register
  180. Transfer Request Generation
  181. Dual-Address Write
  182. Channel Prioritization
  183. Data Transfer
  184. Channel Termination
  185. UART Module Features
  186. Serial Communication Channel
  187. UART Module Signal Definitions
  188. Request-To-Send
  189. Baud-Rate Generator/Timer
  190. Transmitter
  191. Receiver
  192. Receiver FIFO
  193. Looping Modes
  194. Local Loopback Mode
  195. Multidrop Mode
  196. Bus Operation
  197. Mode Register 1 (UMR1n)
  198. Mode Register 2 (UMR2n)
  199. Status Registers (USRn)
  200. Clock-Select Registers (USCRn)
  201. Command Registers (UCRn)
  202. Reset Transmitter
  203. Transmitter Enable
  204. Receiver Buffer Registers (UBRn)
  205. Input Port Change Registers (UIPCRn)
  206. Interrupt Status Registers (UISRn)
  207. Interrupt Mask Registers (UIMRn)
  208. Baud Rate Generator (MSB) Register (UBG1n)
  209. Output Port Data Registers (UOP1n)
  210. Programming
  211. UART Module Initialization Sequence
  212. Features
  213. Internal Bus Interface
  214. QSPI RAM
  215. Transmit RAM
  216. Baud Rate Selection
  217. Transfer Length
  218. QSPI Memory Map and Register Definitions
  219. QSPI Delay Register (QDLYR)
  220. QSPI Interrupt Register (QIR)
  221. QSPI Address Register (QAR)
  222. Command RAM Registers (QCR0–QCR15)
  223. Programming Example
  224. Audio Interface Overview
  225. Audio Interface Block Diagram
  226. Audio Interface Structure
  227. Audio Interface Memory Map and Register Definitions
  228. Audio Interrupt Mask and Status Register Descriptions
  229. IIS/EIAJ Transmitter Descriptions
  230. IIS/EIAJ Transmitter Interrupts
  231. Digital Audio Interface (EBU/SPDIF) Register Descriptions
  232. IEC958 Receive Interface
  233. Control Channel Interrupt (IEC958 "C" Channel New Frame)
  234. EBU Extracted Clock
  235. U and Q Receive Register Interrupts
  236. Behavior of User Channel Receive Interface (non-CD data)
  237. Transmit "C" Channel
  238. CD Subcode Interrupts
  239. Free Running Counter Synchronization
  240. Data Exchange Register Descriptions
  241. Data Exchange Register Overview
  242. Data In Selection
  243. PDIR and PDOR Field Formatting
  244. Overrun and Underrun with PDIR and PDOR Registers
  245. audioGlob Register Descriptions
  246. Audio Interrupts
  247. PDOR1, PDOR2, and PDOR3 Interrupts
  248. Audio Interrupt Routines and Timing
  249. CD-ROM Block Encoder and Decoder Register Descriptions
  250. CD-ROM Decoder Interrupts
  251. CD-ROM Encoder Interrupts
  252. Phase/Frequency Determination and XTRIM Function
  253. Filtering for the Discrete Time Oscillator
  254. XTRIM Internal Logic
  255. START Signal
  256. Repeated START Signal
  257. Handshaking
  258. Generation of START
  259. Post-Transfer Software Response
  260. Generation of Repeated START
  261. Arbitration Lost
  262. Boot ROM Operation
  263. Boot Type Detection
  264. Serial Boot Data Format
  265. Supported Commands
  266. Boot from UART
  267. Creating Appropriate Boot Record Files
  268. Debug Support Signals
  269. Breakpoint (BKPT)
  270. Processor Status Clock (PSTCLK)
  271. Processor Status Signal Encoding
  272. Begin Execution of Taken Branch (PST = )
  273. Begin Execution of RTE Instruction (PST = )
  274. CPU Halt
  275. BDM Serial Interface
  276. Receive Packet Format
  277. BDM Command Set
  278. Command Sequence Diagram
  279. Command Set Descriptions
  280. Write Address/Data Register (WAREG and WDREG)
  281. Write Memory Location (WRITE)
  282. Dump Memory Block (DUMP)
  283. Fill Memory Block (FILL)
  284. Resume Execution (GO)
  285. Read Control Register (RCREG)
  286. Write Control Register (WCREG)
  287. Read Debug Module Register (RDMREG)
  288. Unassigned Opcodes
  289. Real-Time Debug Support
  290. Theory of Operation
  291. Emulator Mode
  292. Debug Module Hardware
  293. Address Breakpoint Registers
  294. Address Attribute Trigger Register
  295. Program Counter Breakpoint Register (PBR, PBMR)
  296. Data Breakpoint Registers (DBR, DBMR)
  297. Trigger Definition Register (TDR)
  298. Configuration/Status Register (CSR)
  299. BDM Address Attribute Register (BAAR)
  300. Freescale-Recommended BDM Pinout
  301. JTAG Signal Descriptions
  302. Test Clock (TCK)
  303. Test Data Input/Development Serial Input (TDI/DSI)
  304. JTAG Register Definitions
  305. SAMPLE/PRELOAD Instruction
  306. BYPASS Instruction
  307. JTAG Boundary Scan Register
  308. Obtaining the IEEE 1149.1A Standard
  309. Introduction
  310. ATA DMA Address Register (ATA_DADDR)
  311. USB/FlexCAN Clock Register (USBCANCLK)
  312. Endianness Issues
  313. Modes of Operation
  314. External Signal Description
  315. ATA_DIOR (Out)
  316. Timing on ATA Bus
  317. PIO Mode Timing
  318. Timing in Multiword DMA Mode
  319. UDMA In Timing Diagrams
  320. UDMA Out Timing Diagrams
  321. Memory Map and Register Definitions
  322. Memory Map
  323. Register Descriptions
  324. Timing Registers
  325. TIME_1 Register
  326. TIME_AX Register
  327. TIME_M Register
  328. TIME_K Register
  329. TIME_ZAH Register
  330. TIME_DZFS Register
  331. TIME_CYC Register
  332. FIFO_FILL Register
  333. Interrupt Registers
  334. Interrupt_Pending Register
  335. Interrupt_Enable Register
  336. Interrupt_Clear Register
  337. Drive Registers Connected to ATA Bus
  338. Resetting ATA Bus
  339. Using DMA Mode to Receive Data from ATA Bus
  340. Using DMA Mode to Transmit Data to ATA Bus
  341. Block Diagram
  342. System Clock
  343. Module Identification Registers
  344. General Hardware Parameters (HWGENERAL) Register
  345. Host Hardware Parameters (HWHOST) Register
  346. Transmit Buffer Hardware Parameters (HWTXBUF) Register
  347. Receive Buffer Hardware Parameters (HWRXBUF) Register
  348. Capability Registers
  349. Host Controller Structural Parameters (HCSPARAMS)
  350. Device Controller Interface Version (DCIVERSION)
  351. Operational Registers
  352. USB Status Register (USBSTS)
  353. USB Interrupt Enable Register (USBINTR)
  354. Frame Index Register (FRINDEX)
  355. Control Data Structure Segment Register (CTRLDSSEGMENT)
  356. Device Address Register (DEVICEADDR), Non-EHCI
  357. Endpoint List Address Register (ENDPOINTLISTADDR), Non-EHCI
  358. Master Interface Data Burst Size Register (BURSTSIZE)—Non-EHCI
  359. Transmit FIFO Tuning Controls Register (TXFILLTUNING)—Non-EHCI
  360. Configure Flag Register (CONFIGFLAG)
  361. On-The-Go Status and Control (OTGSC), Non-EHCI
  362. USB Mode Register (USBMODE)—Non-EHCI
  363. Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI
  364. Endpoint Initialization Register (ENDPTPRIME)—Non-EHCI
  365. Endpoint Flush Register (ENDPTFLUSH), Non-EHCI
  366. Endpoint Status Register (ENDPTSTATUS), Non-EHCI
  367. Endpoint Complete Register (ENDPTCOMPLETE), Non-EHCI
  368. Endpoint Control Register n (ENDPTCTRLn), Non-EHCI
  369. FIFO RAM Controller
  370. Periodic Frame List
  371. Asynchronous List Queue Head Pointer
  372. Isochronous (High-Speed) Transfer Descriptor (iTD)
  373. iTD Transaction Status and Control List
  374. iTD Buffer Page Pointer List (Plus)
  375. Split Transaction Isochronous Transfer Descriptor (siTD)
  376. siTD Endpoint Capabilities/Characteristics
  377. siTD Transfer State
  378. siTD Buffer Pointer List (Plus)
  379. siTD Back Link Pointer
  380. Next qTD Pointer
  381. qTD Token
  382. qTD Buffer Page Pointer List
  383. Queue Head Horizontal Link Pointer
  384. Transfer Overlay
  385. Periodic Frame Span Traversal Node (FSTN)
  386. FTSN Normal Path Pointer
  387. Host Controller Initialization
  388. Power Port
  389. Port Suspend/Resume
  390. Schedule Traversal Rules
  391. Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries
  392. Periodic Schedule
  393. Managing Isochronous Transfers Using iTDs
  394. Software Operational Model for iTDs
  395. Periodic Scheduling Threshold
  396. Asynchronous Schedule
  397. Adding Queue Heads to Asynchronous Schedule
  398. Removing Queue Heads from Asynchronous Schedule
  399. Empty Asynchronous Schedule Detection
  400. Asynchronous Schedule Traversal: Start Event
  401. Buffer Pointer List Use for Data Streaming with qTDs
  402. Adding Interrupt Queue Heads to the Periodic Schedule
  403. Ping Control
  404. Split Transactions
  405. Asynchronous—Do-Start-Split
  406. Split Transaction Interrupt
  407. Host Controller Operational Model for FSTNs
  408. Software Operational Model for FSTNs
  409. Tracking Split Transaction Progress for Interrupt Transfers
  410. Periodic Interrupt—Do-Start-Split
  411. Periodic Interrupt—Do-Complete-Split
  412. Managing the QH[FrameTag] Field
  413. Rebalancing the Periodic Schedule
  414. Split Transaction Scheduling Mechanisms for Isochronous
  415. Tracking Split Transaction Progress for Isochronous Transfers
  416. Split Transaction Execution State Machine for Isochronous
  417. Periodic Isochronous—Do Complete Split
  418. Complete-Split for Scheduling Boundary Cases 2a, 2b
  419. Split Transaction for Isochronous—Processing Examples
  420. Port Test Modes
  421. Interrupts
  422. Transfer/Transaction Based Interrupts
  423. Data Buffer Error
  424. USB Interrupt (Interrupt on Completion (IOC))
  425. Host System Error
  426. Endpoint Queue Head
  427. Endpoint Capabilities/Characteristics
  428. Endpoint Transfer Descriptor (dTD)
  429. Device Operational Model
  430. Port State and Control
  431. Bus Reset
  432. Suspend/Resume
  433. Managing Endpoints
  434. Stalling
  435. Data Toggle Inhibit
  436. Priming Receive Endpoints
  437. Interrupt/Bulk Endpoint Bus Response Matrix
  438. Control Endpoint Operation Model
  439. Status Phase
  440. Isochronous Endpoint Operational Model
  441. Isochronous Pipe Synchronization
  442. Managing Queue Heads
  443. Queue Head Initialization
  444. Operational Model For Setup Transfers
  445. Building a Transfer Descriptor
  446. Transfer Completion
  447. Flushing/De-Priming an Endpoint
  448. Servicing Interrupts
  449. Deviations from the EHCI Specifications
  450. Discovery
  451. Operational Model
  452. Asynchronous Transaction Scheduling and Buffer Management
  453. Multiple Transaction Translators
  454. Embedded Design
  455. Port Speed Detection
  456. The CAN System
  457. Module Disabled Mode
  458. Listen-only Mode
  459. FlexCAN Configuration Register (CANMCRn)
  460. FlexCAN Control Register (CANCTRLn)
  461. FlexCAN Free Running Timer Register (TIMERn)
  462. FlexCAN Error Counter Register (ERRCNTn)
  463. FlexCAN Error and Status Register (ERRSTATn)
  464. Interrupt Mask Register (IMASKn)
  465. Message Buffer Structure
  466. Functional Overview
  467. Arbitration Process
  468. Self-Received Frames
  469. Matching Process
  470. Locking and Releasing Message Buffers
  471. CAN Protocol Related Frames
  472. Time Stamp
  473. FlexCAN Initialization Sequence
  474. Miscellaneous Configuration Register (MISCCR)
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