Instruction CacheMCF5253 Reference Manual, Rev. 15-2 Freescale Semiconductor5.3 Instruction Cache Physical OrganizationThe instruction cache is a direct-mapped single-cycle memory, organized as 512 lines, each containing 16Bytes. The memory storage consists of a 512-entry tag array (containing addresses and a valid bit), and thedata array containing 8 Kbyte of instruction data, organized as 2048 × 32 bits.The two memory arrays are accessed in parallel: bits [12:4] of the instruction fetch address provide theindex into the tag array, and bits [12:2] addressing the data array. The tag array outputs the address mappedto the given cache location along with the valid bit for the line. This address field is compared to bits[31:12] of the instruction fetch address from the local bus to determine if a cache hit in the memory arrayhas occurred. If the desired address is mapped into the cache memory, the output of the data array is drivenonto the ColdFire core's local data bus completing the access in a single cycle.The tag array maintains a single valid bit per line entry. Accordingly, only entire 16 byte lines are loadedinto the instruction cache.The instruction cache also contains a 16 byte fill buffer that provides temporary storage for the last linefetched in response to a cache miss. With each instruction fetch, the contents of the line fill buffer areexamined. Thus, each instruction fetch address examines both the tag memory array and the line fill bufferto see if the desired address is mapped into either hardware resource. A cache hit in either the memoryarray or the line-fill buffer is serviced in a single cycle. Because the line fill buffer maintains valid bits ona longword basis, hits in the buffer can be serviced immediately without waiting for the entire line to befetched.If the referenced address is not contained in the memory array or the line-fill buffer, the instruction cacheinitiates the required external fetch operation. In most situations, this is a 16 byte line-sized burst reference.The hardware implementation is a nonblocking design, meaning the ColdFire core's local bus is releasedafter the initial access of a miss. Thus, the cache or the SRAM module can service subsequent requestswhile the remainder of the line is being fetched and loaded into the fill buffer.5.4 Instruction Cache OperationThe instruction cache is physically connected to the ColdFire core local bus, allowing it to service allinstruction fetches from the ColdFire core and certain memory fetches initiated by the debug module.Typically, the debug module's memory references appear as supervisor data accesses but the unit can beprogrammed to generate user-mode accesses and/or instruction fetches. The instruction cache processesany instruction fetch access in the normal manner.5.4.1 Interaction with Other ModulesBecause both the instruction cache and high-speed SRAM module are connected to the ColdFire core localdata bus, certain user-defined configurations can result in simultaneous instruction fetch processing.If the referenced address is mapped into the SRAM module, that module will service the request in a singlecycle. In this case, data accessed from the instruction cache is simply discarded and no external memoryreferences are generated. If the address is not mapped into the SRAM space, the instruction cache handlesthe request in the normal fashion.
