Background Debug Mode (BDM) InterfaceMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 20-27the exact trigger response also programmable. The debug module programming model is accessible fromeither the external development system using the serial interface or from the processor’s supervisorprogramming model using the WDEBUG instruction.20.4.1 Theory of OperationThe breakpoint hardware can be configured to respond to triggers in several ways. The desired responseis programmed into the Trigger Definition Register (TDR). In all situations where a breakpoint triggers,an indication is provided on the DDATA output port, when not displaying captured operands or branchaddresses, as shown in Table 20-17.The breakpoint status is also posted in the CSR.The BDM instructions load and configure the desired breakpoints using the appropriate registers. As thesystem operates, a breakpoint trigger generates a response as defined in the TDR. If the system can toleratethe processor being halted, a BDM-entry can be used. With the TRC bits of the TDR equal to $1, thebreakpoint trigger causes the core to halt as reflected in the PST = $F status.NOTEFor PC breakpoints, the halt occurs before the targeted instruction isexecuted. For address and data breakpoints, the processor may haveexecuted several additional instructions. As a result, trigger reporting isconsidered imprecise.If the processor core cannot be halted, the special debug interrupt can be used. With this configuration,TRC bits of the TDR equal to $2, the breakpoint trigger is converted into a debug interrupt to the processor.This interrupt is treated higher than the nonmaskable level 7 interrupt request. As with all interrupts, it ismade pending until the processor reaches a sample point, which occurs once per instruction. Again, thehardware forces the PC breakpoint to occur immediately (before the execution of the targeted instruction).This is possible because the PC breakpoint comparison is enabled at the same time the interrupt samplingoccurs. For the address and data breakpoints, the reporting is considered imprecise because severaladditional instructions may be executed after the triggering address or data is seen.Once the debug interrupt is recognized, the processor aborts execution and initiates exception processing.At the initiation of the exception processing, the core enters emulator mode. After the standard 8-byteTable 20-17. DDATA[3:0], CSR[31:28] Breakpoint ResponseDDATA[3:0], CSR[31:28] Breakpoint Status$000x No Breakpoints Enabled$001x Waiting for Level 1 Breakpoint$010x Level 1 Breakpoint Triggered$101x Waiting for Level 2 Breakpoint$110x Level 2 Breakpoint TriggeredAll other encodings are reserved for future use.
