Synchronous DRAM Controller ModuleMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 7-3Commands are issued to memory using specific encoding on address and control pins. After system reset,a command must be sent to the SDRAM mode register to configure SDRAM operating parameters.NOTESynchronous operation is selected by setting DCR[SO], DRAM controllerregisters reflect the synchronous operation.7.2.1 DRAM Controller Signals in Synchronous ModeTable 7-2 shows the behavior of DRAM signals in synchronous mode.Figure 7-2 shows a typical signal configuration for synchronous mode.Figure 7-2. MCF5253 SDRAM Interface7.3 SDRAM Memory Map and Register DefinitionsThe memory map is shown in Table 7-3. Field and bit descriptions are shown in the following sections.Table 7-2. Synchronous DRAM Signal ConnectionsSignal DescriptionSDRAS Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by theSDRAM. SDRAS should be connected to the corresponding SDRAM SRAS.SDCAS Synchronous column address strobe. Indicates a valid column address is present and can be latched by theSDRAM. SDCAS should be connected to the corresponding signal labeled SCAS on the SDRAM.SDWE DRAM read/write. Asserted for write operations and negated for read operations.SD_CS0 Chip Select for the SDRAM memory block connected to the MCF5253.BCLKE Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables anddisables the clock internal to SDRAM. When BCLKE is low, memory can enter a power-down mode whereoperations are suspended or they can enter self-refresh mode. BCLKE functionality is controlled by DCR[COC].For designs using external multiplexing, setting COC allows BCLKE to provide command-bit functionality.UDQMLDQMColumn address strobe. For synchronous operation, UDQM, LDQM function as byte enables to the SDRAMs.They connect to the DQM signals (or mask qualifiers) of the SDRAMs.BCLK Bus clock output. Connects to the CLK input of SDRAMs.BCLKA[31:0]U/L DQMSDWESDCASSDRASBCLKE CKECASRASDQMWEADDRESSDATACLKMCF5253D[31:16]SDRAMCSSD_CS0
