Background Debug Mode (BDM) InterfaceMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 20-13debug module initiates a memory read operation. Any serial transfers that begin while the memory accessis in progress return the “not ready” response.Results are returned in the two serial transfer cycles following the completion of the memory access. Thedata transmitted to the debug module during the final transfer is the opcode for the following command.If a memory or register access is terminated with a bus error, the error status (S=1, DATA=$0001) isreturned in place of the result data.20.3.4.1 Command Set DescriptionsThe BDM command set is summarized in Table 20-5. Subsequent sections contain detailed descriptionsof each command.NOTEThe BDM status bit (S) is zero for normally-completed commands, whileillegal commands, “not ready” responses and bus-error transfers return alogic one in the S bit. Refer to Section 20.3.2, “BDM Serial Interface,” forinformation on the serial packet receive packet format.Unassigned command opcodes are reserved by Freescale for future expansion. All unused commandformats within any revision level perform a NOP and return the ILLEGAL command response.20.3.4.1.1 Read Address/Data Register (RAREG/RDREG)RAREG and RDREG reads the selected address or data register and return the 32-bit result. A bus errorresponse is returned if the CPU core is not halted.Figure 20-8. Command/Result FormatsCommand Sequence:Figure 20-9. Read A/D Register Command SequenceOperand Data:NoneNext CMD“Not Ready”Next CMDLS ResultBERRRAREG/RDREG???XXXMS ResultXXX
