IEEE 1149.1 Test Access Port (JTAG)MCF5253 Reference Manual, Rev. 1Freescale Semiconductor 21-7and other part identification data. The IDcode register has been implemented in accordance with IEEE1149.1A so that the least significant bit of the shift register stage is set to logic 1 on the rising edge of TCKfollowing entry into the capture-DR state. Therefore, the first bit to be shifted out after selecting the IDcoderegister is always a logic 1. The remaining 31-bits are also set to fixed values (see Section 21.5.2, “ID CodeRegister”) on the rising edge of TCK following entry into the capture-DR state.The IDCODE instruction is the default value placed in the instruction register when a JTAG reset isaccomplished by either asserting TRST or holding TMS high while clocking TCK through at least fiverising edges and the falling edge after the fifth rising edge. A JTAG reset will cause the TAP state machineto enter the test-logic-reset state (normal operation of the TAP state machine into the test-logic-reset statewill also result in placing the default value of 1 into the instruction register). The shift register portion ofthe instruction register is loaded with the default value of 1 when in the Capture-IR state and a rising edgeof TCK occurs.21.5.1.3 SAMPLE/PRELOAD InstructionThe SAMPLE/PRELOAD instruction provides two separate functions. First, it obtains a sample of thesystem data and control signals present at the MCF5253 input pins and just prior to the boundary scan cellat the output pins. This sampling occurs on the rising edge of TCK in the capture-DR state when aninstruction encoding of 2 is resident in the instruction register. Users can observe this sampled data byshifting it through the boundary-scan register to the output TDO by using the shift-DR state. Both the datacapture and the shift operation are transparent to system operation. Users are responsible for providingsome form of external synchronization to achieve meaningful results because there is no internalsynchronization between TCK and the SYSCLK.The second function of the SAMPLE/PRELOAD instruction is to initialize the boundary scan registerupdate cells before selecting EXTEST or CLAMP. This is achieved by ignoring the data being shifted outof the TDO pin while shifting in initialization data. The update-DR state in conjunction with the fallingedge of TCK can then transfer this data to the update cells. This data will be applied to the external outputpins when one of the instructions listed above is applied.21.5.1.4 CLAMP InstructionThe CLAMP instruction selects the bypass register and asserts functional reset while simultaneouslyforcing all output pins and bidirectional pins configured as outputs to the fixed values that are preloadedand held in the boundary-scan update registers. This instruction enhances test efficiency by reducing theoverall shift path to a single bit (the bypass register) while conducting an EXTEST type of instructionthrough the boundary-scan register. The CLAMP instruction becomes active on the falling edge of TCKin the update-IR state when the data held in the instruction-shift register is equivalent to 3.21.5.1.5 HIGHZ InstructionThe HIGHZ instruction anticipates the need to backdrive the output pins and protect the input pins fromrandom toggling during circuit board testing. The HIGHZ instruction selects the bypass register, forcingall output and bidirectional pins to the high-impedance state.
