Advanced Technology Attachment Controller (ATA)MCF5253 Reference Manual, Rev. 123-4 Freescale SemiconductorIt is the task of the host CPU or the host smart DMA unit to read data or write data to the FIFO tokeep the transfer going. Normal set-up is that the host (smart) DMA unit takes on this task. For thispurpose, the fifo_rcv_alarm and fifo_tx_alarm signals are sent to the host DMA unit.fifo_rcv_alarm informs the host DMA unit that there is at least 1 packet of data waiting in the FIFOto be read by the host DMA. Whenever this signal is high, the host DMA should transfer one packetof data from the FIFO to the main memory. Typical packet size is 32 bytes (8 long words), but otherpacket sizes can be handled too. fifo_tx_alarm informs the host DMA unit that there is space for atleast 1 packet to be written by the host DMA. Whenever this signal is high, the host DMA shouldtransfer one packet of data from main memory to the FIFO. Typical packet size is 32 bytes (8 longwords), but other packet sizes can be handled too.23.4 External Signal DescriptionSee Table 23-1 for the list of signals entering and exiting this module to peripherals within the device.23.4.1 Detailed Signal DescriptionsFor a detailed description of the ATA bus signal, refer to the ATA-6 specification.23.4.1.1 ATA_RST (Out)This signal is the ATA reset signal. When low, the ATA bus is in reset state. When high, no reset. The ATAbus is in reset whenever the appropriate bit in the control register is cleared. After system reset, the ATAbus is in reset.Table 23-1. Signal PropertiesName Function Reset State DirectionATA_RST ATA bus reset signal. Active low. If active,ata device is reset 11 This signal is a standard ATA bus signal. It conforms with the ATA specification.0 OATA_DIOR ATA bus read strobe 1 OATA_DIOW ATA bus write strobe 1 OATA_CS1 ATA bus chip select 1 1 OATA_CS0 ATA bus chip select 0 1 OATA_A2 ATA bus address line 2 0 OATA_A1 ATA bus address line 1 0 OATA_A0 ATA bus address line 0 0 OATA_DMARQ ATA bus DMA request – IATA_DMACK ATA bus DMA acknowledge 1 OATA_INTRQ ATA bus interrupt request – IATA_IORDY ATA bus iordy – OATA_D[15:0] ATA data bus (little-endian) HI_Z Tri-state I/O
