Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-24 Freescale Semiconductor24.6.3.7 Device Address Register (DEVICEADDR), Non-EHCIThis register is not defined in the EHCI specification. The upper seven bits of this register represent thedevice address. After any controller reset or a USB reset, the device address is set to the default address(0). The default address will match all incoming addresses. The software shall reprogram the address afterreceiving a SET_ADDRESS descriptor.This register is shared between the host and device mode functions. In device mode, it is theDEVICEADDR register; in host mode, it is the PERIODICLISTBASE register. See Section 24.6.3.6,“Periodic Frame List Base Address Register (PERIODICLISTBASE),” for more information.24.6.3.8 Current Asynchronous List Address Register (ASYNCLISTADDR)This 32-bit register contains the address of the next asynchronous queue head to be executed by the host.Bits [4–0] of this register cannot be modified by the system software and always return zeros when read.Note that on the USB OTG module, this register is shared between the host and device mode functions. Inhost mode, it is the ASYNCLISTADDR register; in device mode, it is the ENDPOINTLISTADDRregister. See Section 24.6.3.9, “Endpoint List Address Register (ENDPOINTLISTADDR), Non-EHCI,”for more information.Address MBAR2 0x754 (Device Mode) Access: User read/write31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R USBADRWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 015 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 24-19. Device Address (DEVICEADDR) RegisterTable 24-21. Device Address (DEVICEADDR) Register Field DescriptionsField Description31–25USBADRDevice Address. This field corresponds to the USB device address.24–0 Reserved.
