ColdFire CoreMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 3-53.2.3 Supervisor Memory Map and Register DescriptionOnly system programmers use the supervisor programming model to implement sensitive operatingsystem functions, I/O control, and memory management. All accesses that affect the control features ofColdFire processors are in the supervisor memory map and register descriptions, which consists of theregisters available to users as well as the following control registers:• 16-bit status register (SR)• 32-bit vector base register (VBR)Figure 3-3. Supervisor Memory MapAdditional registers may be supported on a part-by-part basis.The following sections describe the supervisor register descriptions.3.2.3.1 Status Register (SR)The SR stores the processor status and includes the CCR, the interrupt priority mask, and other controlbits. In the supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits areaccessible (CCR). The control bits indicate the following states for the processor: trace mode (T-bit),supervisor or user mode (S bit), and master or interrupt state (M).Load AccExtensions01 MOV.L {Ry,#imm},Raccext01 Loads the accumulator 0,1 extension bytes with a 32-bitoperandLoad AccExtensions23 MOV.L {Ry,#imm},Raccext23 Loads the accumulator 2,3 extension bytes with a 32-bitoperandStore AccExtensions01 MOV.L Raccext01,Rx Writes the contents of accumulator 0,1 extension bytes into a CPUregisterStore AccExtensions23 MOV.L Raccext23,Rx Writes the contents of accumulator 2,3 extension bytes into a CPUregisterSystem Byte Condition Code Register (CCR)15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0T 0 S M 0 I [2–0] 0 0 0 X N Z V CFigure 3-4. Status RegisterTable 3-3. eMAC Instruction Summary (continued)Command Mnemonic Description31–20 19–0MUST BE ZEROS VBR VECTOR BASE REGISTER15– 8 7–0System Byte CCR SR STATUS REGISTER
