DMA ControllerMCF5253 Reference Manual, Rev. 114-14 Freescale SemiconductorIn the event of a termination error, the BES (DSR[5]) and DONE bit (DSR[0]) are set and no further DMAtransactions take place.14.6.1.2 Dual-Address WriteThe DMA controller module drives the value in the destination address register (DAR) onto the addressbus. If the DINC bit (DCR[19]) is set, then the DAR increments by the appropriate number of bytes at thecompletion of a successful write cycle. The byte count register (BCR) decrements by the appropriatenumber of bytes. The DONE bit (DSR[0]) is set when the BCR reaches zero. If the BCR is greater thanzero, then another read/write transfer is initiated. If the byte count register (BCR) is a multiple of theprogrammed bandwidth control (BWC), then the DMA request signal is negated until termination of thebus cycle to allow the internal arbiter to switch masters.In the event of a termination error, the BES (DSR[5]) and DONE bit (DSR[0]) are set and no further DMAtransactions takes place.14.7 DMA Transfer Functional DescriptionIn the following section, the term DMA request implies that the START bit (DCR[16]) is set or the EEXTbit (DCR[30]) is set, followed by assertion of REQUEST. The START bit is cleared when the channelbegins an internal access.Before initiating a transfer, the DMA controller module verifies that the source size (SSIZE = DSC[21:20])and destination size (DSIZE = DSR[18:17]) for dual-address access are consistent with the source addressand destination address. The CE bit is also set if inconsistency is found between the destination size andthe source size in the BCR for dual-address access. If a misalignment is detected, no transfer occurs andthe configuration error bit (CE = DSR[6]) is set. Depending on the configuration of the DCR, an interruptevent may be issued when the CE bit is set.NOTEIf the auto-align bit (AA = DCR[28]) is set, error checking is performed onthe appropriate registers only.A read/write transfer refers to a dual-address access in which a number of bytes are read from the sourceaddress and written to the destination address. The number of bytes in the transfer is determined by thelarger of the sizes specified by the source and destination size encoding. See Table 14-10 and Table 14-11.The source and destination address registers (SAR and DAR) increment at the completion of a successfuladdress phase. The BCR decrements at the completion of a successful address write phase. A successfuladdress phase occurs when a valid address request is not held by the arbiter.14.7.1 Channel Initialization and StartupBefore starting a block transfer operation, the channel registers must be initialized with informationdescribing the channel configuration, request-generation method, and data block. This initialization isaccomplished by programming the appropriate information into the channel registers.
