MCF5253 Reference Manual, Rev. 1Freescale Semiconductor 4-1Chapter 4Phase-Locked Loop and Clock DividersThis chapter provides detailed information about the operation and programming of the clock generationmodule as well as the recommended circuit settings. It also describes the audio clock generation and thesystem power states.4.1 PLL Features• The PLL locks to the crystal clock at the CRIN pin and produces a processor clock (PSTCLK) anda SYSCLK which is always 1/2 of the processor clock.• The audio clock (AUDIOCLK) can be derived directly from CRIN or from theLRCK3/AUDIOCLK/GPIO43 input pin.• The Audio DAC Master clocks MCLK1 and MCLK2 are derived directly from CRIN.• The PLL is configured by writing to a configuration register.• The PLL Configuration Register must always be programmed to Bypass mode before it isreprogrammed to change any clock frequency. In bypass mode, the crystal clock is fed to theprocessor (PSTCLK).• When the PLL is switched from “bypass” to “normal operation”, the switch-over is delayed untilthe PLL is locked.• The MCF5253 has a new block added to the output of the PLL / Clock Dividers to provideglitch-free Dynamic Clock Switching. This allows dynamic switching of the clock rate being fedto the CPU core and the system bus. This new block is controlled by a new 32-bit register calledthe ClockRate Register.Figure 4-1 shows the PLL module and the frequency relationships of various clock signals.
