UART ModulesMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 15-13programming bit 2 of UMR1. UMR1 should also be programmed before enabling the transmitter andloading the corresponding data bits into the transmit buffer.In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether itis enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and loads the character into thereceiver holding register FIFO, provided the received A/D bit is a one (address tag). The character isdiscarded if the received A/D bit is a zero (data tag). If the receiver is enabled, all received characters aretransferred to the CPU using the receiver holding register stack during read operations.In either case, the data bits are loaded into the data portion of the stack while the A/D bit is loaded into thestatus portion of the stack normally used for a parity error (USR bit 5). Framing error, overrun error, andbreak detection operate normally. The A/D bit takes the place of the parity bit; therefore, parity is neithercalculated nor checked. Messages in this mode can still contain error detection and correction information.One way to provide error detection, if 8-bit characters are not required, is to use software to calculate parityand append it to the 5-, 6-, or 7-bit character.15.3.5 Bus OperationThis section describes the operation of the bus during read, write, and interrupt- acknowledge cycles to theUART module. All UART module registers must be accessed as bytes.15.3.5.1 Read CyclesThe CPU accesses the UART module with 1 to 2 wait states because the core system clock is divided by2 for the UART module. The UART module responds to reads with byte data on D[7:0]. Reserved registersreturn logic zero during reads.15.3.5.2 Write CyclesThe CPU with zero wait states accesses the UART module. The UART module accepts write data onD[7:0]. Write cycles to read-only registers and reserved registers complete in a normal manner withoutexception processing; however, the data is ignored.15.3.5.3 Interrupt Acknowledge CyclesThe UART module can arbitrate for interrupt servicing and supply the interrupt vector when it hassuccessfully won arbitration. The vector number must be provided if interrupt servicing is necessary; thus,the interrupt vector register (UIVR) must be initialized. The interrupt vector number generated by the IVRis used if the autovector is not enabled in the SIM Interrupt Control Register (ICR). If the UIVR is notinitialized and the ICR is not programmed for autovector, a spurious interrupt exception is taken ifinterrupts are generated. This works in conjunction with the MCF5253 interrupt controller, which allowsa programmable Interrupt Priority Level (IPL) for the interrupt.15.4 UART Memory Map and Register DefinitionsThis section contains a detailed description of each register and its specific function as well as flowchartsof basic UART module programming.
