IEEE 1149.1 Test Access Port (JTAG)MCF5253 Reference Manual, Rev. 1Freescale Semiconductor 21-921.5.3 JTAG Boundary Scan RegisterThe MCF5253 model includes an IEEE 1149.1A-compliant boundary-scan register. The boundary-scanregister is connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instructions areselected. This register captures signal pin data on the input pins, forces fixed values on the output signalpins, and selects the direction and drive characteristics (a logic value or high impedance) of thebidirectional and tri-state signal pins. A detailed description of the boundary scan register bits for theMCF5253 is part of the BDSL file.21.5.4 JTAG Bypass RegisterThe MCF5253 includes an IEEE 1149.1A-compliant bypass register, which creates a single bit shiftregister path from TDI to the bypass register to TDO when the BYPASS instruction is selected.21.6 RestrictionsThe test logic is implemented using static logic design, and TCK can be stopped in either a high or lowstate without loss of data. The system logic, however, operates on a different system clock which is notsynchronized to TCK internally. Any mixed operation requiring the use of IEEE 1149.1A test logic inconjunction with system functional logic that uses both clocks, must have coordination andsynchronization of these clocks done externally to the MCF5253.21.7 Disabling IEEE 1149.1A Standard OperationThere are two ways to use the MCF5253 without the IEEE 1149.1A test logic being active:1. Non-use of the JTAG test logic by either non-termination (disconnection) or intentional fixing ofTAP logic values.2. Intentional disabling of the JTAG test logic by setting TEST[2:0]= 001 (entering Debug mode).There are several considerations that must be addressed if the IEEE 1149.1A logic is not going to be usedonce the MCF5253 is assembled onto a board.The prime consideration is to ensure that the IEEE 1149.1A test logic remains transparent and benign tothe system logic during functional operation. This requires the minimum of either connecting the TRSTpin to logic 0, or connecting the TCK clock pin to a clock source that will supply five rising edges and thefalling edge after the fifth rising edge, to ensure that the part enters the test-logic-reset state. Therecommended solution is to connect TRST to logic 0.Another consideration is that the TCK pin does not have an internal pullup as is required on the TMS, TDI,and TRST pins; therefore, it should not be left unterminated to preclude mid-level input values.Figure 21-4 shows pin values recommended for disabling JTAG with the MCF5253 in JTAG mode.
