ColdFire CoreMCF5253 Reference Manual, Rev. 13-12 Freescale Semiconductor3.5.11 Fault-on-Fault HaltIf a CF2 processor encounters any type of fault during the exception processing of another fault, theprocessor immediately halts execution with the catastrophic “fault-on-fault” condition. A reset is requiredto force the processor to exit this halted state.3.5.12 Reset ExceptionAsserting the reset input signal to the processor causes a reset exception. The reset exception has thehighest priority of any exception; it provides for system initialization and recovery from catastrophicfailure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannotbe recovered.The reset exception places the processor in the supervisor mode by setting the S bit and disables tracingby clearing the T bit in the SR. This exception also clears the M bit and sets the processor’s interruptpriority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero ($00000000). Thecontrol registers specifying the operation of any memories (e.g., cache and/or RAM modules) connecteddirectly to the processor are disabled.NOTEOther implementation-specific supervisor registers are also affected.Refer to each of the modules in this manual for details on these registers.After reset is negated, the core performs two longword read bus cycles. The first longword at address 0 isloaded into the stack pointer and the second longword at address 4 is loaded into the program counter. Afterthe initial instruction is fetched from memory, program execution begins at the address in the PC. If anaccess error or address error occurs before the first instruction is executed, the processor enters thefault-on-fault halted state.3.6 Instruction Execution TimingThis section describes CF2 processor instruction execution times in terms of processor core clock cycles.The number of operand references for each instruction is enclosed in parentheses following the number ofclock cycles. Each timing entry is presented as C(r/w) where:• C—number of processor clock cycles, including all applicable operand fetches and writes, and allinternal core cycles required to complete the instruction execution.• r/w—number of operand reads (r) and writes (w) required by the instruction. An operationperforming a read-modify-write function is denoted as (1/1).This section includes the assumptions concerning the timing values and the execution time details.3.6.1 Timing AssumptionsFor the timing data presented in this section, the following assumptions apply:1. The operand execution pipeline (OEP) is loaded with the opword and all required extension wordsat the beginning of each instruction execution. This implies that the OEP does not wait for theinstruction fetch pipeline (IFP) to supply opwords and/or extension words.
