DMA ControllerMCF5253 Reference Manual, Rev. 114-6 Freescale SemiconductorNOTEOnly part of the on-chip SRAM can be accessed by the DMA. The memorycontrolled by RAMBAR0 is not visible for DMA. The memory controlledby RAMBAR1 is visible for DMA. As a result, the SAR or DAR addressrange cannot be programmed to on-chip SRAM0 memory, since the on-chipDMAs cannot access on-chip SRAM0 as a source or destination. They canaccess SRAM1, however.14.4.3 Destination Address RegisterThe destination address register (DAR) is a 32-bit register containing the address to which the DMAcontroller module sends data during a transfer.Address MBAR + $300MBAR+ $340MBAR + $380MBAR + $3C0Access: User read/write31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R SAR31 SAR30 SAR29 SAR28 SAR27 SAR26 SAR25 SAR24 SAR23 SAR22 SAR21 SAR20 SAR19 SAR18 SAR17 SAR16WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 015 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R SAR15 SAR14 SAR13 SAR12 SAR11 SAR10 SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 SAR0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 14-4. Source Address Register (SAR)Address MBAR + $304MBAR + $344MBAR + $384MBAR + $3C4Access: User read/write31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R DAR31 DAR30 DAR29 DAR28 DAR27 DAR26 DAR25 DAR24 DAR23 DAR22 DAR21 DAR20 DAR19 DAR18 DAR17 DAR16WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 015 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R DAR15 DAR14 DAR13 DAR12 DAR11 DAR10 DAR9 DAR8 DAR7 DAR6 DAR5 DAR4 DAR3 DAR2 DAR1 DAR0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 14-5. Destination Address Register (DAR)
