Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-46 Freescale SemiconductorThe DMA controllers must access both control information and packet data from DMA cache memory.The control information is contained in link list based queue structures. The DMA controllers have statemachines that are able to parse data structures defined in the EHCI specification. In host mode, the datastructures are EHCI compliant and represent queues of transfers to be performed by the host controller,including the split-transaction requests that allow an EHCI controller to direct packets to FS and LS speeddevices. In device mode, the data structures designed to be similar to those in the EHCI specification andare used to allow device responses to be queued for each of the active pipes in the device.The DMA controller can access only the DMA_CACHE memory. Therefore, all data and data structuresthat are read/written by the DMA engine must be reside in this memory. The USB module has priority onthis memory and will get access 1 clock cycle after the request.24.7.2 FIFO RAM ControllerThe FIFO RAM controller is used for context information and to control FIFOs between the protocolengine and the DMA controller. These FIFOs decouple the system processor/memory bus requests fromthe extremely tight timing required by USB.The use of the FIFO buffers differs between host and device mode operation. In host mode, a single datachannel is maintained in each direction through the buffer memory. In device mode, multiple FIFOchannels are maintained for each of the active endpoints in the system.In host mode, the module uses a 256-byte TX buffer and a 128-byte RX buffer. Device operation uses asingle 128-byte RX buffer and a 64-byte TX buffer for each endpoint.24.7.3 PHY InterfaceThe module interfaces to the internal PHY. The primary function of the port controller block is to isolatethe rest of the module from the transceiver, and to move all of the transceiver signaling into the primaryclock domain of the module. This allows the module to run synchronously with the system processor andit's associated resources.24.8 Host Data StructuresThis section defines the interface data structures used to communicate control, status, and data betweenHCD (software) and the Enhanced Host Controller (hardware). The data structure definitions in thissection support a 32-bit memory buffer address space. The interface consists of a Periodic Schedule,Periodic Frame List, Asynchronous Schedule, Isochronous Transaction Descriptors, Split-transactionIsochronous Transfer Descriptors, Queue Heads, and Queue Element Transfer Descriptors.The periodic frame list is the root of all periodic (isochronous and interrupt transfer type) support for thehost controller interface. The asynchronous list is the root for all the bulk and control transfer type support.Isochronous data streams are managed using Isochronous Transaction Descriptors. Isochronoussplit-transaction data streams are managed with Split-transaction Isochronous Transfer Descriptors. AllInterrupt, Control, and Bulk data streams are managed via queue heads and Queue Element TransferDescriptors. These data structures are optimized to reduce the total memory footprint of the schedule andto reduce (on average) the number of memory accesses needed to execute a USB transaction.
