Queued Serial Peripheral Interface (QSPI) ModuleMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 16-7choose to delay a standard period after serial transfer is complete or can specify a delay period. Writing avalue to QDLYR[DTL] specifies a delay period. The DT bit in command RAM determines whether thestandard delay period (DT = 0) or the specified delay period (DT = 1) is used. The following expressionis used to calculate the delay:Delay after transfer = 32 × QDLYR[DTL] /SYSCLK frequency (DT = 1)where QDLYR[DTL] has a range of 2 to 255.A zero value for DTL causes a delay-after-transfer value of 8192/SYSCLK frequency.Standard delay after transfer = 17/SYSCLK frequency (DT = 0)Adequate delay between transfers must be specified for long data streams because the QSPI modulerequires time to load a transmit RAM entry for transfer. Receiving devices need at least the standard delaybetween successive transfers. If SYSCLK is operating at a slower rate, the delay between transfers mustbe increased proportionately.16.3.4 Transfer LengthThere are two transfer length options. The user can choose a default value of 8 bits or a programmed valueof 8 to 16 bits inclusive. The programmed value must be written into QMR[BITS]. The bits per transferenable (BITSE) field in the command RAM determines whether the default value (BITSE = 0) or theBITS[3–0] value (BITSE = 1) is used. QMR[BITS] gives the required number of bits to be transferred.16.3.5 Data TransferOperation is initiated by setting QDLYR[SPE]. Shortly after QDLYR[SPE] is set, the QSPI executes thecommand at the command RAM address pointed to by QWR[NEWQP]. Data in transmit RAM is loadedinto the data shift register and transmitted. Data that is simultaneously received is stored in the receiveRAM.When the proper number of bits has been transferred, the QSPI stores the working queue pointer value inQWR[CPTQP], increments the working queue pointer, and loads the next data for transfer from thetransmit RAM. The command pointed to by the incremented working queue pointer is executed nextunless a new value has been written to QWR[NEWQP]. If a new queue pointer value is written while atransfer is in progress, then that transfer is completed normally.When the CONT bit in the command RAM is set, the QSPI_CS signals are asserted between transfers.When CONT is cleared, QSPI_CS[3:0] are negated between transfers. The QSPI_CS signals are not highimpedance.When the QSPI reaches the end of the queue, it asserts QIR[SPIF]. If QIR[SPIFE] is set, an interruptrequest is generated when QIR[SPIF] is asserted. Then the QSPI clears QDLYR[SPE] and stops, unlesswraparound mode is enabled.Wraparound mode is enabled by setting QWR[WREN]. The queue can wrap to pointer address 0x0, or tothe address specified by QWR[NEWQP], depending on the state of QWR[WRTO].
