Bus OperationMCF5253 Reference Manual, Rev. 18-10 Freescale SemiconductorFigure 8-7. Back-to-Back Bus Cycle8.5.5 Burst CyclesWhen burst read enable or burst write enable is asserted into the relevant chip select register, the MCF5253will initiate burst cycles any time a transfer size is larger than the port size the MCF5253 is transferring to.A line transfer to a 16-bit port would constitute a burst cycle of eight words of data.The MCF5253 bus can support 3-2-2-2 burst cycles to maximize cache performance and optimize DMAtransfers. Users can add wait states if desired by delaying termination of the cycle.Through the chip select control registers, users can enable bursting on reads, bursting on writes or burstingon both reads and writes if desired.8.5.5.1 Line TransfersA line is defined as a 16-byte value, aligned in memory on 16-byte boundaries. Although the line itself isaligned on 16-byte boundaries, the line access does not necessarily begin on the aligned address.Therefore,the bus interface supports line transfers on multiple address boundaries. The allowable patterns during aline access are shown in Table 8-8.8.5.5.2 Line Read Bus CyclesFigure 8-8 shows a line access read with zero wait states.Table 8-8. Allowable Line Access PatternsAddr[3:2] Longword Accesses00 0 - 4 - 8 - C01 4 - 8 - C - 010 8 - C - 0 - 411 C - 0 - 4 - 8BCLKA[31:0]RWD[31:16]TAReadS0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5WriteCSxOE
