MCF5253 Reference Manual, Rev. 1Freescale Semiconductor 22-1Chapter 22USB, ATA DMA, and Clock Integration ModuleThis chapter includes the memory map, register descriptions and functional description of the ATA DMAintegration module.22.1 IntroductionThis chapter includes registers that are used to configure the various modules that are new to the MCF5253family. It also includes a shared 16 kB local memory for the ATA and USB modules.22.2 Memory Map and Register DefinitionsTable 22-1 provides the memory map and register definitions for the ATA DMA integration module.22.2.1 Miscellaneous Configuration Register (MISCCR)Table 22-1. Real Time Clock Memory MapMBAR2Offset Register Access Reset Value Section/Page0x500 Miscellaneous Configuration Register (MISCCR) R/W Undefined 22.2.1/22-10x504 ATA DMA Source and Destination Address Register (ATA_DADDR) R/W 0x0000_0000 22.2.2/22-30x508 ATA DMA Count Register (ATA_DCOUNT) R/W 0x0000_0000 22.2.3/22-30x50C RTC Time Register (RTC_TIME) R Undefined 26.3.2/26-20x510 USB/FlexCAN Clock Gating (USBCANCLK) R/W 0x0000_0000 22.2.5/22-4Offset: MBAR2 0x500 (MISCCR) Access: User read/write31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16RWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 015 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R URIP 0 URIE RTCPL RTCCLRDMAENDCPUENDADIP ADIE ADTD ADTAW URIC ADICReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 22-1. Miscellaneous Configuration Register (MISCCR)
