I 2 C ModulesMCF5253 Reference Manual, Rev. 118-12 Freescale Semiconductor18.5.5 I 2C Data I/O Registers (MBDR)When an address and R/W bit is written to the MBDR and the I2C is the master, a transmission will start.When data is written to the MBDR, a data transfer is initiated. The most significant bit is sent first in bothcases. In the master-receive mode, reading the MBDR register allows the read to occur but also initiatesnext byte data receiving. In slave mode, the same function is available after it is addressed.18.6 I2 C Programming Examples18.6.1 Initialization SequenceA reset places the I 2C Control Register into default status. Before the interface can transfer serial data,users must perform an initialization procedure as follows:1. Update the Frequency Divider Register (MFDR) and select the required division ratio to obtainSCL frequency from the system bus clock.2. Update the I 2C Address Register (MADR) to define its slave address.3. Set the IEN bit of the I 2C Control Register (MBCR) to enable the I2C bus interface system.4. Modify the MBCR to select master/slave mode, transmit/receive mode, and interrupt-enable or not.1IIFThe I2 C Interrupt (IIF) bit is set when an interrupt is pending, which will cause a processor interrupt request (providedIIEN is set). IIF is set when one of the following events occurs:• Complete one byte transfer (set at the falling edge of the 9th clock)• Receive a calling address that matches its own specific address in slave-receive mode• Arbitration lostThis bit must be cleared by software by writing a zero to it in the interrupt routine.0RXAKThe value of SDA during the acknowledge bit of a bus cycle. If the received acknowledge bit (RXAK) is low, it indicatesan acknowledge signal has been received after the completion of 8 bits data transmission on the bus. If RXAK is high,it means no acknowledge signal has been detected at the 9th clock.1 No acknowledge received0 Acknowledge receivedAddress MBAR+$290 (MBDR)MBAR2+$450 (MBDR2)Access: Supervisor or User read/write7 6 5 4 3 2 1 0R D7 D6 D5 D4 D3 D2 D1 D0WReset 0 0 0 0 0 0 0 0Figure 18-8. MBDR RegisterTable 18-6. MBSR Register Field DescriptionsField Description
