System Integration Module (SIM)MCF5253 Reference Manual, Rev. 19-22 Freescale Semiconductor9.7.1.1 Internal Arbitration OperationPARK register field bits [1:0] are programmed to indicate the priority of internal transfers. The possiblemasters that can initiate internal transfers are the core and the on-chip DMAs. Since the priority betweenDMAs is resolved by their relative priority amongst each other and by programming the BWC bits in theirrespective DMA control registers (see Section 14.4, “DMA Memory Map and Register Definitions”), theMPARK bits need only arbitrate priority between the core and the DMA module (which contains all fourDMA channels) for internally generated transfers.There are four arbitration schemes that the MPARK[1:0] bits can be programmed to with respect tointernally generated transfers. The following summarizes these schemes when EARBCTRL=0:1. Round Robin Scheme (PARK[1:0]=00)—In this scenario, depending on which master has priorityin the current transfer, the other master has priority in the next transfer once the current master hasfinished. When the processor is initialized, the core has first priority.So for example, if the core is the bus master and is finishing a bus transfer and DMA channels0 and 1 (both set to BWC=010) are asserting an internal bus request signal, then the DMAchannel 0 would gain ownership of the bus after the core; but after channel 0 finishes itstransfer, the core would have ownership of the bus if its request was asserted.NOTEThe Internal DMA has higher priority than the ColdFire Core if the internalDMA has its bandwidth BWC[2:0] bits set to 000 (maximum bandwidth).2. Park on Master Core Priority (PARK[1:0]=01)—Any time arbitration is occurring or the bus is idle,the core has priority. The DMA module can arbitrate a transfer only when the core’s internal busrequest signal is negated.3. Park on Master DMA Priority (PARK[1:0]=10)—Any time arbitration is occurring or the bus isidle, the DMA has priority. The core can arbitrate a transfer only when the DMA’s internal busrequest signal is negated.4. Park on Current Master Priority (PARK[1:0]=11)—Whatever the current master is, they havepriority. Only when the bus is idle can the other master gain ownership and priority of the bus. Forexample, if out of reset the core has priority it will continue to have priority until the bus becomesidle. Then when the DMA asserts its internal bus request signal, it will then have priority.Address MBAR + $0c Access: User read/write7 6 5 4 3 2 1 0R PARK[1] PARK[0] IARBCTRL EARBCTRL SHOWDATA BCR24BITWReset 0 0 0 0 0 0 0 0Figure 9-14. Default Bus Master Register (MPARK)
