FlexCAN ModuleMCF5253 Reference Manual, Rev. 125-16 Freescale Semiconductor25.5.7 Interrupt Mask Register (IMASKn)IMASKn contains one interrupt mask bit per buffer. It enables the CPU to determine which buffer willgenerate an interrupt after a successful transmission/reception (that is, when the corresponding IFLAGnbit is set).25.5.8 Interrupt Flag Register (IFLAGn)IFLAGn contains one interrupt flag bit per buffer. Each successful transmission/reception sets thecorresponding IFLAGn bit and, if the corresponding IMASKn bit is set, will generate an interrupt.The interrupt flag is cleared by writing a 1, while writing 0 has no effect.2BOFFINTBus off interrupt. Used to request an interrupt when the FlexCAN enters the bus off state. The user must write a 1to clear this bit. Writing 0 has no effect.0 No bus off interrupt requested.1 This bit is set when the FlexCAN state changes to bus off. If the CANCTRLn[BOFFMSK] bit is set an interruptrequest is generated. This interrupt is not requested after reset.1ERRINTError interrupt. Indicates that at least one of the ERRSTATn[15:10] bits is set. The user must write a 1 to clear thisbit. Writing 0 has no effect.0 No error interrupt request.1 At least one of the error bits is set. If the CANCTRLn[ERRMSK] bit is set, an interrupt request is generated.0 Reserved, should be cleared.Offset MBAR2 0x1028 (IMASK0) Access: User read/write31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R BUFnM, n=31–0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 25-10. FlexCAN Interrupt Mask (IMASKn) RegisterTable 25-9. FlexCAN Interrupt Mask (IMASKn) Register Field DescriptionsField Description31–0BUFnMBuffer interrupt mask. Enables the respective FlexCAN message buffer (MB0 to MB31) interrupt. These bits allowthe CPU to designate which buffers will generate interrupts after successful transmission/reception.0 The interrupt for the corresponding buffer is disabled.1 The interrupt for the corresponding buffer is enabled.Note: Setting or clearing an IMASKn bit can assert or negate an interrupt request, if the corresponding IFLAGn bitit is set.Table 25-8. FlexCAN Error and Status (ERRSTATn) Register Field Descriptions (continued)Field Description
