Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-70 Freescale Semiconductorregister, the host controller also generates an interrupt on the resume event. The software acknowledgesthe resume event interrupt by clearing the Port Change Detect status bit in the USBSTS register.[1] Hardware interrupt issued if Port Change Interrupt Enable bit in the USBINTR register is set.[2] PME# asserted if enabled (Note: PME Status must always be set).[3] PME# not asserted.24.9.5 Schedule Traversal RulesThe host controller executes transactions for devices using a simple, shared-memory schedule. Theschedule is comprised of a few data structures, organized into two distinct lists. The data structures aredesigned to provide the maximum flexibility required by USB and minimize memory traffic andhardware/software complexity.The system software maintains two schedules for the host controller: a periodic schedule and anasynchronous schedule. The root of the periodic schedule is the PERIODICLISTBASE register. SeeSection 24.6.3.6, “Periodic Frame List Base Address Register (PERIODICLISTBASE),” for moreinformation. The PERIODICLISTBASE register is the physical memory base address of the periodicframe list. The periodic frame list is an array of physical memory pointers. The objects referenced fromthe frame list must be valid schedule data structures as defined in Section 24.8, “Host Data Structures.” InTable 24-63. Behavior During Wake-up EventsPort Status and Signaling Type Signaled Port ResponseDevice StateD0 not D0Port disabled, resume K-State received No Effect N/A N/APort suspended, Resume K-State received Resume reflected downstream on signaled port. Force PortResume status bit in PORTSC register is set. Port ChangeDetect bit in USBSTS register is set.[1], [2] [2]Port is enabled, disabled or suspended, andthe port's WKDSCNNT_E bit is set. Adisconnect is detected.Depending in the initial port state, the PORTSC Connect andEnable status bits are cleared, and the Connect Change statusbit is set. Port Change Detect bit in the USBSTS register is set.[1], [2] [2]Port is enabled, disabled or suspended, andthe port's WKDSCNNT_E bit is cleared. Adisconnect is detected.Depending on the initial port state, the PORTSC Connect andEnable status bits are cleared, and the Connect Change statusbit is set. Port Change Detect bit in the USBSTS register is set.[1], [3] [3]Port is not connected and the port'sWKCNNT_E bit is a one. A connect isdetected.PORTSC Connect Status and Connect Status Change bits areset. Port Change Detect bit in the USBSTS register is set.[1], [2] [2]Port is not connected and the port'sWKCNNT_E bit is a zero. A connect isdetected.PORTSC Connect Status and Connect Status Change bits areset. Port Change Detect bit in the USBSTS register is set.[1], [3] [3]Port is connected and the port's WKOC_Ebit is a one. An over-current conditionoccurs.PORTSC Over-current Active, Over-current Change bits are set.If Port Enable/Disable bit is a one, it is cleared. Port ChangeDetect bit in the USBSTS register is set[1], [2] [2]Port is connected and the port's WKOC_Ebit is a zero. An over-current conditionoccurs.PORTSC Over-current Active, Over-current Change bits are set.If Port Enable/Disable bit is a one, it is cleared. Port ChangeDetect bit in the USBSTS register is set.[1], [3] [3]
