I 2 C ModulesMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 18-5Each data byte is 8 bits long. Data can be changed only while SCL is low and must be held stable whileSCL is high, as shown in Figure 18-2 There is one clock pulse on SCL for each data bit with the MSBbeing transferred first. Each byte of data must be followed by an acknowledge bit, which is signalled fromthe receiving device by pulling the SDA low at the ninth clock. One complete data byte transfer needs nineclock pulses.If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. Themaster can then generate a stop signal to abort the data transfer or a start signal (repeated start) to start anew calling sequence.If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means “endof data'’ to the slave. The slave releases the SDA line for the master to generate a STOP or START signal.18.4.4 Repeated START SignalAs shown in Figure 18-2, a repeated START signal is a START signal generated without first generatinga STOP signal to terminate the communication. The master uses this method to communicate with anotherslave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.18.4.5 STOP SignalThe master can terminate the communication by generating a STOP signal to free the bus. However, themaster can generate a START signal followed by a calling command without generating a STOP signalfirst. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA whileSCL is at logical 1 (see Figure 18-2).NOTEA master can generate a STOP even if the slave has made anacknowledgment at which point the slave must release the bus.18.4.6 Arbitration ProcedureI2C is a true multimaster bus that allows connection to more than one master. If two or more masters tryto simultaneously control the bus, a clock synchronization procedure determines the bus clock, for whichthe low period is equal to the longest clock low period and the high is equal to the shortest one among thedevices. A data arbitration procedure determines the relative priority of the contending masters. A busmaster loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing mastersimmediately switch over to slave-receive mode and stop driving SDA output. In this case, the transitionfrom master to slave mode does not generate a STOP condition. Meanwhile, hardware sets MBSR[IAL]to indicate loss of arbitration.18.4.7 Clock SynchronizationBecause wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects all thedevices connected on the bus. The devices start counting their low period when the master drives the SCLline low. Once a device clock has gone low, it holds the SCL line low until the clock high state is reached.However, the change of low to high in the MCF5253 clock may not change the state of the SCL line if
