Background Debug Mode (BDM) InterfaceMCF5253 Reference Manual, Rev. 120-12 Freescale Semiconductor20.3.4 Command Sequence DiagramA command sequence diagram (see Figure 20-7) shows the serial bus traffic for each command. Eachbubble in the diagram represents a single 17-bit transfer across the bus. The top half in each bubblecorresponds to the data transmitted by the development system to the debug module; the bottom halfcorresponds to the data returned by the debug module in response to the previous development systemcommands. Command and result transactions are overlapped to minimize latency.Figure 20-7. Command Sequence DiagramThe cycle in which the command is issued contains the development system command mnemonic (in thisexample, “read memory location”). During the same cycle, the debug module responds with either thelow-order results of the previous command or a command complete status (if no results were required).During the second cycle, the development system supplies the high-order 16 bits of the memory address.The debug module returns a “not ready” response unless the received command was decoded asunimplemented, in which case the response data is the illegal command encoding. If an illegal commandresponse occurs, the development system should retransmit the command.NOTEThe “not ready” response can be ignored unless a memory-referencing cycleis in progress. Otherwise, the debug module can accept a new serial transferafter 32 processor clock periods.In the third cycle, the development system supplies the low-order 16 bits of a memory address. The debugmodule always returns the “not ready” response in this cycle. At the completion of the third cycle, theNext CMDReadMemoryLocation“Not Ready”Next CMDLS ResultBERRXXX“Not Ready”Next CMD“Not Ready”LS Addr“Not Ready”XXX“Illegal”MS Addr“Not Ready”Read (Long)???Commands Transmitted to the Debug ModuleCommand Code Transmitted During This CycleResponses from the Debug ModuleResults From Previous CommandXXXMS ResultXXXHigh-Order 16 Bits of Memory AddressLow-Order 16 Bits of Memory AddressNon-Serial Related ActivitySequence Taken IfOperation Has NotCompletedNextModeCommandData Unused FromThis TransferSequence Taken if Illegal Commandis Received by Debug Module Sequence Taken if BusError Occurs OnMemory AccessHigh and Low-Order16 Bits of Results
