IDE and Flash Media InterfaceMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 13-1313.5.2 Flash Media Interface OperationThe Flash Media interface is built around two Interface Shift Registers, each of which work independently.Figure 13-10 shows a block diagram of one interface shift register.Figure 13-10. Shift RegisterTable 13-9. Flash Media Configuration Register Field DescriptionsField Description Res31–22 Reserved –21–20CARDTYPECard Type00 Sony Memory Stick01 SecureDigital, 1-bit serial data11 SecureDigital, 4-bit serial data019RECEIVEEDGEReceive Edge11 Receive data on falling edge of SCLKOUT pin0 Receive data on rising edge of SCLKOUT pin1 In SD mode, this bit should be programmed 1. In MemoryStick mode, programming 1 gives more relaxed timing, howeverMemory Stick specs stipulate it should be 0.018 Reserved 017–16STOPCLOCKStop Clock300 Normal operation01 Freeze clock low10 Freeze clock high0115–8CLOCKCOUNT1CLOCKCOUNT1+12, 3 is the sclk_out_pin high period in number of bus clocks 157–0CLOCKCOUNT0CLOCKCOUNT0+12, 3 is the sclk_out_pin low period in number of bus clocks2 The clock generator will increase the length of some SCLKOUT clock cycles to avoid bus contention when the SDIO pinswitches from input to output, or from output to input mode. The clock generator will stop the SCLKOUT clock if this isnecessary to avoid buffer overrun or buffer underrun.3 It is acceptable to reprogram these bits while the interface is running. No glitch will occur on sclk_out.15InterfaceShiftRegisterBS (MemoryStick mode only)Serial dataCommandBitsbitCountershift_busyint_levelcrc_is_0TxBufferEmptyRcvBufferFullloadTxShiftRegstoreRcvShiftRegstopclock(to clock generator)RxBufferFull
