FlexCAN ModuleMCF5253 Reference Manual, Rev. 125-4 Freescale SemiconductorOnce entry into freeze mode is requested, the FlexCAN waits until an intermission or idle condition existson the CAN bus, or until the FlexCAN enters the error passive or bus off state. Once one of theseconditions exists, the FlexCAN waits for the completion of all internal activity such as arbitration,matching, move-in, and move-out. When this happens, the following events occur:• The FlexCAN stops transmitting/receiving frames.• The prescaler is disabled, thus halting all CAN bus communication.• The FlexCAN ignores its Rx pins and drives its Tx pins as recessive.• The FlexCAN loses synchronization with the CAN bus and the NOTRDY and FRZACK bits inCANMCRn are set.• The CPU is allowed to read and write the error counter registers (in other modes they areread-only).After engaging one of the mechanisms to place the FlexCAN in freeze mode, the user must wait for theFRZACK bit to be set before accessing any other registers in the FlexCAN; otherwise, unpredictableoperation may occur. In freeze mode, all memory mapped registers are accessible.To exit freeze mode, the BKPT line must be negated or the HALT bit in CANMCRn must be cleared. Oncefreeze mode is exited, the FlexCAN will resynchronize with the CAN bus by waiting for 11 consecutiverecessive bits before beginning to participate in CAN bus communication.25.3.2.3 Module Disabled ModeThis mode disables the FlexCAN module; it is entered by setting CANMCRn[MDIS]. If the module isdisabled during freeze mode, it shuts down the system clocks, sets the LPMACK bit, and clears theFRZACK bit.If the module is disabled during transmission or reception, FlexCAN does the following:• Waits to be in either idle or bus-off state, or else waits for the third bit of intermission and thenchecks it to be recessive• Waits for all internal activities such as arbitration, matching, move-in, and move-out to finish• Ignores its Rx input pin and drives its Tx pin as recessive• Shuts down the system clocksThe bus interface unit continues to operate, enabling the CPU to access memory-mapped registers, exceptthe free-running timer, the error counter register, and the message buffers, which cannot be accessed whenthe module is disabled. Exiting from this mode is done by negating the MDIS bit, which will resume theclocks and negate the LPMACK bit.25.3.2.4 Loop-back ModeThe module enters this mode when the LPB bit in the control register is set. In this mode, FlexCANperforms an internal loop back that can be used for self test operation. The bit stream output of thetransmitter is internally fed back to the receiver input. The Rx CAN input pin is ignored and the Tx CANoutput goes to the recessive state (logic 1). FlexCAN behaves as it normally does when transmitting andtreats its own transmitted message as a message received from a remote node. In this mode, FlexCAN
