UART ModulesMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 15-1715.4.3 Status Registers (USRn)The USR registers indicate the status of the characters in the receive FIFO and the status of the transmitterand receiver. The RB, FE, and PE bits are cleared by the Reset Error Status command in the UCR registersif the RB bit has not been read. Also, RB, FE, PE and OE can also be cleared by reading the Receive buffer(URB).Table 15-6. Mode Register 2 (UMR2n) Field DescriptionsField Description7–6CMChannel mode.Selects a channel mode. Section 15.3.3, “Looping Modes,” describes individual modes.00 Normal01 Automatic echo10 Local loop-back11 Remote loop-back5TxRTSTransmitter ready-to-send.Controls negation of RTS to automatically terminate a message transmission when the transmitter is disabled aftercompletion of a transmission. Attempting to program a receiver and transmitter in the same channel for RTS controlis not permitted and disables RTS control for both.0 The transmitter has no effect on RTS.1 When the transmitter is disabled after transmission completes, setting this bit automatically clears UOP[RTS] onebit time after any characters in the channel transmitter shift and holding registers are completely sent, includingthe programmed number of stop bits.Note: Not available on UART2.4TxCTSTransmitter clear-to-send.If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the transmitter.0 CTS has no effect on the transmitter.1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character.If CTS is asserted, the character is sent; if it is negated, the channel TxD remains in the high state andtransmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect itstransmission.Note: Not available on UART23–0SBStop-bit length control.Selects the length of the stop bit appended to the transmitted character. Stop-bit lengths of 9/16th to 2 bits areprogrammable for 6–8 bit characters. Lengths of 1 1/16th to 2 bits are programmable for 5-bit characters. In all cases,the receiver checks only for a high condition at the center of the first stop-bit position, that is, one bit time after thelast data bit or after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, clearing bit 3selects one stop bit and setting bit 3 selects 2 stop bits for transmission.SB 5 Bits 6–8 Bits SB 5 Bits 6–8 Bits0000 1.063 0.563 1000 1.563 1.5630001 1.125 0.625 1001 1.625 1.6250010 1.188 0.688 1010 1.688 1.6880011 1.250 0.750 1011 1.750 1.7500100 1.313 0.813 1100 1.813 1.8130101 1.375 0.875 1101 1.875 1.8750110 1.438 0.938 1110 1.938 1.9380111 1.500 1.000 1111 2.000 2.000
