Advanced Technology Attachment Controller (ATA)MCF5253 Reference Manual, Rev. 123-6 Freescale SemiconductorThis electrical spec must be met for the pads used on the ATA I/Os if no bus buffers and bus transceiversare used.Alternative is to use bus buffers. This is the only way to operate the ATA interface if 3.3 V or 5.0 Vcompatibility on the ATA bus is wanted, and no 3.3 V or 5.0 V tolerant pads on the device are available.The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factorswill make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fastUDMA mode operation is needed, this may not be compatible with bus buffers.Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns witha 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.23.4.3 Timing on ATA BusTiming on the ATA bus is explained in this section. It is also explained how to make sure the ATA interfacemeets timing. Timing is explained with timing figures and also equations are provided that need to befulfilled for the host to meet timing.23.4.3.1 Timing ParametersIn the timing equations, some timing parameters are used. These parameters depend on the implementationof the ATA interface on silicon, the bus buffer used, the cable delay and cable skew. Refer to Table 23-2for the list of parameters used to specify the ATA timing.Table 23-2. Timing ParametersName Meaning Controlled byT Bus clock period clock generatorti_ds Set-up time ATA_Dx to ATA_IORDY edge (UDMA-in only) top level designti_dh hold time ATA_IORDY edge to ATA_Dx (UDMA-in only) top level designtco Propagation delay bus clock L-to-H to the following signals:ATA_CS0, ATA_CS1. ATA_CS2. ATA_A2. ATA_A1, ATA_A0, ATA_DIOR, ATA_DIOW,ATA_DMACK, ATA_Dxtop level designtsu Setup time ATA_Dx to bus clock L-to-H top level designtsui Setup time ATA_IORDY to bus clock H-to-L top level designthi Hold time ATA_IORDY to bus clock H to L top level designtskew1 Max difference in propagation delay bus clock L-to-H to any of following signals:ATA_CS0, ATA_CS1. ATA_CS2. ATA_A2. ATA_A1, ATA_A0, ATA_DIOR, ATA_DIOW,ATA_DMACK, ATA_Dx (write)top level designtskew2 Max difference in buffer propagation delay for any of following signals:ATA_CS0, ATA_CS1. ATA_CS2. ATA_A2. ATA_A1, ATA_A0, ATA_DIOR, ATA_DIOW,ATA_DMACK, ATA_Dx (write)transceivertskew3 Max difference in buffer propagation delay for any of following signals:ATA_IORDY, ATA_Dx (read)transceivertbuf Max buffer propagation delay transceivertcable1 Cable propagation delay for ATA_Dx cabletcable2 Cable propagation delay for control signals:ATA_DIOR, ATA_DIOW, ATA_IORDY, ATA_DMACKcable
