Background Debug Mode (BDM) InterfaceMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 20-7• The read/write control register commands, RCREG and WCREG use the register coding schemefrom the MOVEC instruction.• The read/write debug module register commands, RDMREG and WDMREG support debugmodule register accesses.• Illegal command responses can be returned using the FILL and DUMP commands, if notimmediately preceded by certain, specific BDM commands.• For any command performing a byte-sized memory read operation, the upper 8 bits of the responsedata are undefined. The referenced data is returned in the lower 8 bits of the response.• The debug module forces alignment for memory-referencing operations: long accesses are forcedto a 0-modulo-4 address; word accesses are forced to a 0-modulo-2 address. An address errorresponse is never returned.20.3.1 CPU HaltAlthough many BDM operations can occur in parallel with CPU operation, unrestricted BDM operationrequires the CPU to be halted. A number of sources can cause the CPU to halt, including the following asshown in order of priority:1. The occurrence of the catastrophic fault-on-fault condition automatically halts the processor.2. The occurrence of a hardware breakpoint can be configured to generate a pending halt condition ina manner similar to the assertion of the BKPT signal. In all cases, the assertion of this type of haltis first made pending in the processor. Next, the processor samples for pending halt and interruptconditions once per instruction. Once the pending condition is asserted, the processor haltsexecution at the next sample point. See Section 20.4.1, “Theory of Operation,” for more detail.3. The execution of the HALT ColdFire instruction immediately suspends execution. By default thisis a supervisor instruction and attempted execution while in user mode generates a privilegeviolation exception. A User Halt Enable (UHE) control bit is provided in the Configuration/StatusRegister (CSR) to allow execution of HALT in user mode. The processor may be restarted after theexecution of the HALT instruction by serial shifting a “GO” command into the debug module.Execution continues at the instruction following the HALT opcode.4. The assertion of the BKPT input pin is treated as a pseudo-interrupt. For example, the haltcondition is made pending until the processor core samples for halts/interrupts. The processorsamples for these conditions once during the execution of each instruction. If there is a pendinghalt condition at the sample time, the processor suspends execution and enters the halted state.There are two special cases involving the assertion of the BKPT pin to be considered.After the system reset signal is negated, the processor waits for 16 clock cycles before beginning resetexception processing. If the BKPT input pin is asserted within the first eight cycles after RSTI is negated,the processor enters the halt state, signaling that halt status, ($F), on the PST outputs. While in this state,all resources accessible through the debug module can be referenced. This is the only opportunity to forcethe ColdFire processor into emulation mode using the EMU bit in the configuration/status register (CSR).Once the system initialization is complete, the processor response to a BDM GO command is dependenton the set of BDM commands performed while breakpointed. Specifically, if the processor’s PC register
