Signal DescriptionMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 2-132.23.1 Test ModeThe TEST[2:0] inputs are used for various manufacturing and debug tests. For normal mode TEST [2:1]should be ways be tied low. TEST0 should be set high for BDM debug mode and set low for JTAG mode.2.23.2 High ImpedanceThe assertion of HI_Z will force all output drivers to a high-impedance state. The timing on HI_Z isindependent of the clock.NOTEJTAG operation will override the HI_Z pin.2.23.3 Processor Clock OutputThe internal PLL generates this PSTCLK/GPIO51 and output signal, and is the processor clock output thatis used as the timing reference for the Debug bus timing (DDATA[3:0] and PST[3:0]). ThePSTCLK/GPIO51 is at the same frequency as the core processor.2.23.4 Debug DataThe debug data pins, DDATA0/CTS1/SDATA0_SDIO1/GPIO1, DDATA1/RTS1/SDATA2_BS2/GPIO2,DDATA2/CTS0/GPIO3, and DDATA3/RTS0/GPIO4, are four bits wide. This nibble-wide bus displayscaptured processor data and break-point status. Refer to Chapter 20, “Background Debug Mode (BDM)Interface,” for additional information on this bus.2.23.5 Processor StatusThe processor status pins, PST0/GPIO50, PST1/GPIO49, PST2/INTMON/GPIO48, andPST3/INTMON/GPIO47, indicate the MCF5253 processor status. During debug mode, the timing issynchronous with the processor clock (PSTCLK) and the status is not related to the current bus transfer.Table 2-13 shows the encodings of these signals..Table 2-13. Processor Status Signal EncodingsPST[3:0]Definition(Hex) (Binary)$0 0000 Continue execution$1 0001 Begin execution of an instruction$2 0010 Reserved$3 0011 Entry into user-mode$4 0100 Begin execution of PULSE and WDDATA instructions$5 0101 Begin execution of taken branch or Synch_PC 1$6 0110 Reserved
