Queued Serial Peripheral Interface (QSPI) ModuleMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 16-3• 16 transmit data words (transfer RAM)• 16 receive data words (transfer RAM)RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word of receivedata comprise 1 queue entry.The user initiates QSPI operation by loading a queue of commands in command RAM, writing transmitdata into transmit RAM, and then enabling the QSPI data transfer. The QSPI executes the queuedcommands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to signal theircompletion. Optionally, QIR[SPIFE] can be enabled to generate an interrupt.The QSPI uses four queue pointers. The user can access three of them through fields in QSPI WrapRegister (QWR):• The new queue pointer, QWR[NEWQP], points to the first command in the queue.• An internal queue pointer points to the command currently being executed.• The completed queue pointer, QWR[CPTQP], points to the last command executed.• The end queue pointer, QWR[ENDQP], points to the final command in the queue.The internal pointer is initialized to the same value as QWR[NEWQP]. During normal operation, thefollowing sequence repeats:1. The command pointed to by the internal pointer is executed.2. The value in the internal pointer is copied into QWR[CPTQP].3. The internal pointer is incremented.Execution continues at the internal pointer address unless the QWR[NEWQP] value is changed. After eachcommand is executed, QWR[ENDQP] and QWR[CPTQP] are compared. When a match occurs,QIR[SPIF] is set and the QSPI stops unless wraparound mode is enabled. Setting QWR[WREN] enableswraparound mode.QWR[NEWQP] is cleared at reset. When the QSPI is enabled, execution begins at address 0x0 unlessanother value has been written into QWR[NEWQP]. QWR[ENDQP] is cleared at reset but is changed toshow the last queue entry before the QSPI is enabled. QWR[NEWQP] and QWR[ENDQP] can be writtenat any time. When the QWR[NEWQP] value changes, the internal pointer value also changes unless atransfer is in progress, in which case the transfer completes normally. Leaving QWR[NEWQP] andQWR[ENDQP] set to 0x0 causes a single transfer to occur when the QSPI is enabled.Data is transferred relative to QSPI_CLK which can be generated in any one of four combinations of phaseand polarity using QMR[CPHA, CPOL]. Data is transferred most significant bit (msb) first. The numberof bits transferred defaults to eight, but can be set to any value from 8 to 16 by writing a value into theBITSE field of the command RAM, QCR[BITSE].16.3.1 QSPI RAMThe QSPI contains an 80-byte block of static RAM that can be accessed by both the user and the QSPI.This RAM does not appear in the MCF5253 memory map because it can only be accessed by the userindirectly through the QSPI address register (QAR) and the QSPI data register (QDR).
