Signal DescriptionMCF5253 Reference Manual, Rev. 12-14 Freescale Semiconductor2.24 BDM/JTAG SignalsThe MCF5253 complies with the IEEE 1149.1A JTAG testing standard. The JTAG test pins aremultiplexed with background debug pins. See Chapter 20, “Background Debug Mode (BDM) Interface,”for details.2.25 Clock and Reset SignalsThese signals configure the MCF5253 and provide interface signals to the external system.2.25.1 Reset InAsserting RSTI causes the MCF5253 to enter reset exception processing. When RSTI is recognized, thedata bus is tri-stated.2.25.2 System Bus InputMCF5253 includes on-chip crystal oscillator. The crystal must be connected between CRIN and CROUT.An externally generated clock signal can also be used and should be connected directly to the CRIN pin.2.26 Wake-Up SignalTo exit power down mode, apply a LOW level to the WAKEUP/GPIO21 input pin.$7 0111 Begin execution of RTE instruction$8 1000 Begin 1-byte data transfer on DDATA$9 1001 Begin 2-byte data transfer on DDATA$A 1010 Begin 3-byte data transfer on DDATA$B 1011 Begin 4-byte data transfer on DDATA$C 1100 Exception processing 2$D 1101 Emulator mode entry exception processing 2$E 1110 Processor is stopped, waiting for interrupt 2$F 1111 Processor is halted 21 Rev. B enhancement.2 These encodings are asserted for multiple cycles.Table 2-13. Processor Status Signal Encodings (continued)PST[3:0]Definition(Hex) (Binary)
