Bus OperationMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 8-15Figure 8-16. Master Reset TimingDuring the master reset period, the data bus is being tri-stated, the address bus is driven to any value, andall other bus signals are driven to their negated state. Once RSTI negates, the bus stays in this state untilthe core begins the first bus cycle for reset exception processing. A master reset causes any bus cycle(including DRAM refresh cycle) to terminate. In addition, master reset initializes registers appropriatelyfor a reset exception.If at power-on reset, the MCF5253 is configured to boot from external memory connected to CS0. ThenCS0 is configured to address the external boot ROM / Flash. The configuration for CS0 at this time ishard-wired inside the MCF5253.Configuration is summarized in Table 8-9.8.7.1 Software Watchdog ResetThe software watchdog reset is performed anytime the executing software does not provide the correctwrite sequence with the enable-control bit set. This reset helps recovery from runaway software ornonterminated bus cycles. During the software watchdog reset period all signals are driven either to a highimpedance state or a negated state as appropriate.Table 8-9. Power-On Reset Configuration for CS0Port Size 16 BitsCycle type Internal termination, 15 wait cyclesBurst inhibit asserted for both read and write cyclesVDDRSTICRIND[31:16]SDRAS, SDCASCS, OE>16CLKIN CYCLESSDWE, BCLKEA[23:1], RW
