MCF5253 Reference Manual, Rev. 1Freescale Semiconductor 16-1Chapter 16Queued Serial Peripheral Interface (QSPI) ModuleThis chapter describes the operation of the Queued Serial Peripheral interface module of the MCF5253and provides its memory map and register descriptions.16.1 FeaturesThe QSPI module provides a serial peripheral interface with queued transfer capability. It allows users toqueue up to 16 transfers at once, eliminating CPU intervention between transfers.• Programmable queue to support up to 16 transfers without user intervention• Supports transfer sizes of 8 to 16 bits in 1-bit increments• Four peripheral chip-select lines for control of up to 15 devices• Programmable baud rates up to 17.5Mbps at a CPU clock of 140 MHz• Programmable delays• Programmable clock phase and polarity• Supports wraparound mode for continuous transfers16.2 QSPI Module OverviewThe QSPI module communicates with the core using internal memory mapped registers starting atMBAR + $400. See Section 16.4, “QSPI Memory Map and Register Definitions.” A block diagram of theQSPI module is shown in Figure 16-1.16.2.1 Interface and PinsThe module supports 4 external CS pins which can be decoded externally to provide control for up to 15devices. There are a total of seven signals: QSPI_Dout, QSPI_Din, QSPI_CLK, QSPI_CS [3:0].Peripheral chip-select signals, QSPI_CS[3:0], are used to select an external device as the source ordestination for serial data transfer. Signals are asserted at a logic level corresponding to the value of theQSPI_CS[3:0] bits in the command RAM whenever a command in the queue is executed. More than onechip-select signal can be asserted simultaneously.Although QSPI_CS[3:0] will function as simple chip selects in most applications, up to 15 devices can beselected by decoding them with an external 4-to-16 decoder.
