Signal DescriptionMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 2-52.2 GPIOMany pins have an optional GPIO function.• General purpose input is always active, regardless of state of pin.• General purpose output or primary output is determined by the appropriate setting of the PinMultiplex Control Registers, GPIO-FUNCTION, GPIO1-FUNCTION and PIN-CONFIG.• At Power-on reset all pins are set to their primary function.2.3 MCF5253 Bus SignalsThe signals discussed in this section provide the external bus interface to the MCF5253.2.3.1 Address BusThe address bus provides the address of the byte or most significant byte of the word or longword beingtransferred.The address lines also serve as the DRAM address pins, providing multiplexed row and columnaddress signals.High Impedance HI_Z Assertion tri-states output signal pins InDebug Data DDATA0/CTS1/SDATA0_SDIO1/GPIO1DDATA1/RTS1/SDATA2_BS2/GPIO2DDATA2/CTS0/GPIO3DDATA3/RTS0/GPIO4Display of captured processor dataand break-point statusesIn/Out Hi_ZProcessor Status PST0/GPIO50PST1/GPIO49PST2/INTMON2/GPIO48PST3/INTMON1/GPIO47Indication of internal processor status. In/Out Hi_ZProcessor clock PSTCLK/GPIO51 Processor clock output Out –Test Clock TCK Clock signal for IEEE 1149.1A JTAG In –Test Reset/Development SerialClockTRST/DSCLK Multiplexed signal that isasynchronous reset for JTAGcontroller. Also, clock input for debugmodule.In –Test Mode Select/BreakPointTMS/BKPT Multiplexed signal that is test modeselect in JTAG mode and a hardwarebreak-point in debug modeIn –Test Data Input/Development SerialInputTDI/DSI Multiplexed serial input for the JTAG orbackground debug module.In –Test DataOutput/DevelopmentSerial OutputTDO/DSO Multiplexed serial output for the JTAGor background debug moduleOut –Table 2-1. MCF5253 Signal Index (continued)Signal Name Mnemonic Function Input/OutputResetState
