Synchronous DRAM Controller ModuleMCF5253 Reference Manual, Rev. 17-8 Freescale Semiconductor7.4 General Synchronous Operation GuidelinesTo reduce system logic and to support a variety of SDRAM sizes, the DRAM controller provides SDRAMcontrol signals as well as a multiplexed row address and column address to the SDRAM.When SDRAM blocks are accessed, the DRAM controller can operate in either burst or continuous pagemode. The following sections describe the DRAM controller interface to SDRAM, the supported bustransfers, and initialization.7.4.1 Address MultiplexingTable 7-7, Table 7-8, Table 7-9, Table 7-10, and Table 7-11 provide a comprehensive, step-by-step methodto determine the correct address line connections for interfacing the MCF5253 to SDRAM. Note: that thereare separate connection tables for 4Mb to 128 Mb devices and 256 Mb devices.Specifically for the 256Mb devices the tables change due to the fact that we need to have a A24 addressline. But with the MCF5253 A24 and A20 are shared on the same pin. This means that when we programthe A20/A24 pin to be A24. We no longer have A20 available to any memory device connected to thememory bus.To use the tables, find the one that corresponds to the number of column address lines on the SDRAM.Most SDRAMs likely have fewer address lines than are shown in the tables, so follow only the connectionsshown until all SDRAM address lines are connected.7 Reserved, should be cleared.6–1AMxAddress modifier masks. Determine which accesses can occur in a given DRAM block.0 Allow access type to hit in DRAM1 Do not allow access type to hit in DRAM0VValid. Cleared at reset to ensure that the DRAM block is not erroneously decoded.0 Do not decode DRAM accesses.1 Registers controlling the DRAM block are initialized; DRAM accesses can be decoded.Table 7-6. DRAM Controller Mask Register (DMR0) Field Descriptions (continued)Bits DescriptionBit Associated Access Type Access DefinitionC/I CPU space/interruptacknowledgeMOVEC instruction or interrupt acknowledge cycleAM Alternate master External or DMA masterSC Supervisor code Any supervisor-only instruction accessSD Supervisor data Any data fetched during the instruction accessUC User code Any user instructionUD User data Any user data
