UART ModulesMCF5253 Reference Manual, Rev. 115-2 Freescale Semiconductor• Independently programmable receiver and transmitter clock source• Programmable data format— Five to eight data bits plus parity— Odd, even, no parity, or force parity— .563 to 2 stop bits in x16 mode (asynchronous)/1or 2 stop bits in synchronous mode• Programmable channel modes:— Normal (full duplex)— Automatic echo— Local loopback— Remote loopback• Automatic wakeup mode for multidrop applications• Four maskable interrupt conditions• Parity, framing, break, and overrun error detection• False start bit detection• Line-break detection and generation• Detection of breaks originating in the middle of a character• Start/end break interrupt/status15.1.1 Serial Communication ChannelThe communication channel provides a full duplex asynchronous receiver and transmitter using anoperating frequency derived from the system clock.The transmitter accepts parallel data from the CPU; converts it to a serial bit stream; inserts the appropriatestart, stop, and optional parity bits; then outputs a composite serial data stream on the channel transmitterserial data output (TxD). Refer to Section 15.3.2.1, “Transmitter,” for additional information.The receiver accepts serial data on the channel receiver serial data input (RxD); converts it to parallelformat; checks for a start bit, stop bit, parity (if any), or any error condition; and transfers the assembledcharacter onto the bus during read operations. The receiver can be polled or interrupt driven. Refer toSection 15.3.2.2, “Receiver,” for additional information.15.1.2 Baud-Rate Generator/TimerThe 16-bit timer, clocked by the system clock, can function as an asynchronous x16 clock. The baud-ratetimer is part of each UART and not related to the ColdFire timer modules.15.1.3 Interrupt Control LogicAn internal interrupt request signal (IRQ) notifies the MCF5253 interrupt controller of an interruptcondition. The output is the logical NOR of all (as many as four) unmasked interrupt status bits in theUART Interrupt Status Register (UISR). The UART Interrupt Mask Register (UIMR) can be programmedto determine which interrupts will be valid in the UISR.
