Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-68 Freescale SemiconductorIn order to communicate with devices via the asynchronous schedule, the system software must write theASYNDLISTADDR register with the address of a control or bulk queue head. The software must thenenable the asynchronous schedule by writing a one to the Asynchronous Schedule Enable bit in theUSBCMD register. In order to communicate with devices via the periodic schedule, the system softwaremust enable the periodic schedule by writing a one to the Periodic Schedule Enable bit in the USBCMDregister. Note that the schedules can be turned on before the first port is reset (and enabled).Any time the USBCMD register is written, the system software must ensure the appropriate bits arepreserved, depending on the intended operation.24.9.2 Power PortThe Port Power Control (PPC) bit in the HCSPARAMS register indicates whether the USB 2.0 hostcontroller has port power control. When the PPC bit is a one, then the host controller supports port powerswitches. Each available switch has an output enable. PPE is controlled based on the state of thecombination bits PPC bit, EHCI Configured (CF)-bit and individual Port Power (PP) bits.24.9.3 Reporting Over-CurrentHost ports by definition are power providers on USB. Whether the ports are considered high- orlow-powered is a platform implementation issue. Each EHCI PORTSC register has an over-current statusand over-current change bit. The functionality of these bits is specified in the USB SpecificationRevision 2.0.In this implementation, however, over-current is not reported to the USB core. Therefore the bits:Over-current Active and Over-current Change in the PORTSC register will be static. The over-currentdetection and limiting logic resides outside the MCF5253. The USB software stack is responsible formonitoring the Over-current condition on the external device.24.9.4 Suspend/ResumeThe host controller provides an equivalent suspend and resume model as that defined for individual portsin a USB 2.0 hub. Control mechanisms are provided to allow the system software to suspend and resumeindividual ports. The mechanisms allow the individual ports to be resumed completely via softwareinitiation. Other control mechanisms are provided to parameterize the host controller's response (orsensitivity) to external resume events. In this discussion, host-initiated, or software-initiated resumes arecalled Resume Events/Actions; bus-initiated resume events are called wake-up events. The classes ofwakeup events are:• Remote-wakeup enabled device asserts resume signaling. In similar kind to USB 2.0 hubs, whenin host mode the host controller responds to explicit device resume signaling and wake up thesystem (if necessary).• Port connect and disconnect. Sensitivity to these events can be turned on or off by using the portcontrol bits in the PORTSC register. An Over-current event will not wake the USB core.Selective suspend is a feature supported by the PORTSC register. It is used to place specific ports into asuspend mode. This feature is used as a functional component for implementing the appropriate power
