Background Debug Mode (BDM) InterfaceMCF5253 Reference Manual, Rev. 120-2 Freescale Semiconductor20.1.1 Breakpoint (BKPT)The BKPT active-low input signal is used to request a manual breakpoint. Its assertion causes the processorto enter a halted state after the completion of the current instruction. The halt status is reflected on theprocessor status (PST) pins as the value $F.20.1.2 Debug Data (DDATA[3:0])These output signals display the hardware register breakpoint status as a default, or optionally, capturedaddress and operand values. The capturing of data values is controlled by the setting of theconfiguration/status register (CSR). Additionally, execution of the WDDATA instruction by the processorcaptures operands which are displayed on DDATA. These signals are updated each processor cycle.20.1.3 Development Serial Clock (DSCLK)This input signal is synchronized internally and provides the clock for the serial communication port to thedebug module. The maximum frequency is 1/5 the speed of the processor’s clock (CLK). At thesynchronized rising edge of DSCLK, the data input on DSI is sampled, and the DSO output changes state.See Figure 20-3 for more information.20.1.4 Development Serial Input (DSI)The input signal is synchronized internally and provides the data input for the serial communication portto the debug module.20.1.5 Development Serial Output (DSO)This signal provides serial output communication for the debug module responses.20.1.6 Processor Status (PST[3:0])These output signals report the processor status. Table 20-1 shows the encoding of these signals. Theseoutputs indicate the current status of the processor pipeline and are not related to the current bus transfer.The PST value is updated each processor cycle.
