Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-80 Freescale Semiconductorto the Asynchronous Schedule Enable bit in the USBCMD register. The software then can poll theAsynchronous Schedule Status bit to determine when the asynchronous schedule has made the desiredtransition. The software must not modify the Asynchronous Schedule Enable bit unless the value of theAsynchronous Schedule Enable bit equals that of the Asynchronous Schedule Status bit.The asynchronous schedule is used to manage all Control and Bulk transfers. Control and Bulk transfersare managed using queue head data structures. The asynchronous schedule is based at theASYNCLISTADDR register. The default value of the ASYNCLISTADDR register after reset is undefinedand the schedule is disabled when the Asynchronous Schedule Enable bit is cleared.The software may only write this register with defined results when the schedule is disabled, for example,Asynchronous Schedule Enable bit in the USBCMD and the Asynchronous Schedule Status bit in theUSBSTS register are cleared. The system software enables execution from the asynchronous schedule bywriting a valid memory address (of a queue head) into this register. Then the software enables theasynchronous schedule by setting the Asynchronous Schedule Enable bit is set. The asynchronousschedule is actually enabled when the Asynchronous Schedule Status bit is set.When the host controller begins servicing the asynchronous schedule, it begins by using the value of theASYNCLISTADDR register. It reads the first referenced data structure and begins executing transactionsand traversing the linked list as appropriate. When the host controller completes processing theasynchronous schedule, it retains the value of the last accessed queue head's horizontal pointer in theASYNCLISTADDR register. Next time the asynchronous schedule is accessed, this is the first datastructure that is serviced. This provides round-robin fairness for processing the asynchronous schedule.A host controller completes processing the asynchronous schedule when one of the following eventsoccur:• The end of a micro-frame occurs.• The host controller detects an empty list condition.• The schedule has been disabled via the Asynchronous Schedule Enable bit in the USBCMDregister.The queue heads in the asynchronous list are linked into a simple circular list as shown in Figure 24-44.Queue head data structures are the only valid data structures that may be linked into the asynchronousschedule. An isochronous transfer descriptor (iTD or siTD) in the asynchronous schedule yields undefinedresults.The maximum packet size field in a queue head is sized to accommodate the use of this data structure forall non-isochronous transfer types. The USB Specification, Revision 2.0 specifies the maximum packetsizes for all transfer types and transfer speeds. The system software should always parameterize the queuehead data structures according to the core specification requirements.24.9.9.1 Adding Queue Heads to Asynchronous ScheduleThis is a software requirement section. There are two independent events for adding queue heads to theasynchronous schedule. The first is the initial activation of the asynchronous list. The second is insertinga new queue head into an activated asynchronous list.
