UART ModulesMCF5253 Reference Manual, Rev. 115-10 Freescale SemiconductorIn either mode, reading the USR does not affect the FIFO. The FIFO is popped only when the receivebuffer is read. The USR should be read prior to reading the receive buffer. If all three of the FIFO receiverholding registers are full when a new character is received, the new character is held in the receiver shiftregister until a FIFO position is available. If an additional character is received during this state, thecontents of the FIFO are not affected. However, the previous character in the receiver shift register is lostand the OE bit in the USR is set when the receiver detects the start bit of the new overrunning character.To support flow control capability, the receiver can be programmed to automatically negate and assertRTS1 . When in this mode, the receiver automatically negates RTS when a valid start bit is detected and theFIFO is full. When a FIFO position becomes available, the receiver asserts RTS. Using this mode ofoperation prevents overrun errors by connecting the RTS to the CTS input of the transmitting device.To use the RTS signals on UART1, the Pin Configuration Register in the SIM must be set up to enable thecorresponding I/O pins for these functions. If the FIFO contains characters and the receiver is disabled, theCPU can still read the characters in the FIFO. If the receiver is reset, the FIFO and all receiver status bits,corresponding output ports, and interrupt request are reset. No additional characters are received until thereceiver is re-enabled.15.3.3 Looping ModesThe UART can be configured to operate in various looping modes as shown in Figure 15-7. These modesare useful for local and remote system diagnostic functions. The modes are described in the followingparagraphs with additional information available in Section 15.4, “UART Memory Map and RegisterDefinitions.”Switching between modes should only be done while the transmitter and receiver are disabled because theselected mode is activated immediately on mode selection, even if this occurs in the middle of charactertransmission or reception. In addition, if a mode is deselected, the device switches out of the modeimmediately, except for automatic echo and remote echo loopback modes. In these modes, the deselectionoccurs just after the receiver has sampled the stop bit (this is also the one-half point). For automatic echomode, the transmitter stays in this mode until the entire stop bit has been retransmitted.15.3.3.1 Automatic Echo ModeIn this mode, the UART automatically retransmits the received data on a bit-by-bit basis. The localCPU-to-receiver communication continues normally but the CPU-to-transmitter link is disabled. While inthis mode, received data is clocked on the receiver clock and retransmitted on TxD. The receiver must beenabled but not the transmitter. Instead, the transmitter is clocked by the receiver clock.Because the transmitter is not active, the TxEMP and TxRDY bits in USR are inactive and data istransmitted as it is received. Received parity is checked but not recalculated for transmission. Characterframing is also checked but stop bits are transmitted as received. A received break is echoed as receiveduntil the next valid start bit is detected.1. CTS and RTS are not available on UART2.
