Background Debug Mode (BDM) InterfaceMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 20-320.1.7 Processor Status Clock (PSTCLK)Since the debug trace port signals transition each processor cycle and are not related to the external busfrequency, an additional signal is output from the ColdFire microprocessor. The PSTCLK signal is adelayed version of the processor’s high-speed clock and its rising-edge is used by the development systemto sample the values on the PST and DDATA output buses. The PSTCLK signal is intended for use in thestandard 26-pin debug connector. See Figure 20-39.If the real-time trace functionality is not being used, the PCD bit of the CSR may be set (CSR[17] = 1) toforce the PSTCLK, PST, and DDATA outputs to be disabled.20.2 Real-Time Trace SupportIn the area of debug functions, one fundamental requirement is support for real-time trace functionality.For example, definition of the dynamic execution path. The ColdFire solution is to include a parallel outputport providing encoded processor status and data to an external development system. This port ispartitioned into two nibbles (4 bits): one nibble allows the processor to transmit information concerningthe execution status of the core (processor status: PST), while the other nibble allows operand data to beTable 20-1. Processor Status EncodingPST[3:0]Definition(Hex) (Binary)$0 0000 Continue execution$1 0001 Begin execution of an instruction$2 0010 Reserved$3 0011 Entry into user-mode$4 0100 Begin execution of PULSE and WDDATAinstructions$5 0101 Begin execution of taken branch or Sync_PC$6 0110 Reserved$7 0111 Begin execution of RTE instruction$8 1000 Begin 1-byte transfer on DDATA$9 1001 Begin 2-byte transfer on DDATA$A 1010 Begin 3-byte transfer on DDATA$B 1011 Begin 4-byte transfer on DDATA$C 1100 Exception processing†$D 1101 Emulator-mode entry exception processing†$E 1110 Processor is stopped, waiting for interrupt†$F 1111 Processor is halted †Note: †These encodings are asserted for multiple cycles.
