Synchronous DRAM Controller ModuleMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 7-57.3.1.2 DRAM Address and Control (DACR0) (Synchronous Mode)The DRAM address and control register (DACR0), shown in Figure 7-4, contain the base address comparevalue and the control bits for the memory block of the DRAM controller. Address and timing are alsocontrolled by bits in DACR0.Table 7-5 describes DACR0 fields.11ISInitiate self-refresh command.0 Take no action or issue a SELFX command to exit self refresh.1 If DCR[COC] = 0, the DRAM controller sends a SELF command to the SDRAMv to put it in low-power, self-refreshstate where they remain until IS is cleared, at which point the controller sends a SELFX command for the SDRAM toexit self-refresh. The refresh counter is suspended while the SDRAM is in self-refresh; the SDRAM controls therefresh period.10–9RTIMRefresh timing. Determines the timing operation of auto-refresh in the DRAM controller. Specifically, it determines thenumber of clocks inserted between a REF command and the next possible ACTV command. This corresponds to tRCin the SDRAM specification.00 3 clocks01 6 clocks1x 9 clocks8–0RCRefresh count. Controls refresh frequency. The number of bus clocks between refresh cycles is (RC + 1) * 16. Refreshcan range from 16–8192 bus clocks to accommodate both standard and low-power DRAMs with bus clock operationfrom less than 2 MHz to greater than 50 MHz.The following example calculates RC for an auto-refresh period for 4096 rows to receive 64 mS of refresh every15.625 μs for each row (625 bus clocks at 40 MHz).# of bus clocks = 625 = (RC field + 1) * 16RC = (625 bus clocks/16) -1 = 38.06, which rounds to 38; therefore, RC = 0x26.Address MBAR+0x108 (DACR0) Access: User read/write31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R BA RE CASL CBM IMRS PS IP PMWReset – – – – – – – – – – – – – – – – 0 – – – – – – – – 0 – – – – – –Figure 7-4. DRAM Address and Control Register (DACR0) (Synchronous Mode)Table 7-5. DRAM Address and Control Register (DACR0) Field Descriptions (Synchronous Mode)Field Description31–18BABase address register. With DMR[BAM], determines the address range in which the associated DRAM block islocated. Each BA bit is compared with the corresponding address of the current bus cycle. If all unmasked bits match,the address hits in the associated DRAM block.17–16 Reserved, should be cleared.Table 7-4. DRAM Control Register (DCR) Field Descriptions (Synchronous Mode) (continued)Field Description
