Instruction CacheMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 5-35.4.2 Memory Reference AttributesFor every memory reference the ColdFire core or the debug module generates, a set of “effectiveattributes” is determined based on the address and the Access Control Registers (ACR0, ACR1). This setof attributes includes the cacheable/noncacheable definition, the precise/imprecise handling of operandwrite, and the write-protect capability.In particular, each address is compared to the values programmed in the Access Control Registers (ACR).If the address matches one of the ACR values, the access attributes from that ACR are applied to thereference. If the address does not match either ACR, then the default value defined in the Cache ControlRegister (CACR) is used. The specific algorithm is as follows:if (address = ACR0_address including mask)Effective Attributes = ACR0 attributeselse if (address = ACR1_address including mask)Effective Attributes = ACR1 attributeselse Effective Attributes = CACR default attributes5.4.3 Cache Coherency and InvalidationThe instruction cache does not monitor ColdFire core data references for accesses to cached instructions.Therefore, software must maintain cache coherency by invalidating the appropriate cache entries aftermodifying code segments.The cache invalidation can be performed in two ways. The assertion of bit 24 in the CACR forces the entireinstruction cache to be marked as invalid. The invalidation operation requires 512 cycles because the cachesequences through the entire tag array, clearing a single location each cycle. Any subsequent instructionfetch accesses are postponed until the invalidation sequence is complete.The privileged CPUSHL instruction can invalidate a single cache line. When this instruction is executed,the cache entry defined by bits[12:4] of the source address register is invalidated, provided bit 28 of theCACR is cleared.These invalidation operations can be initiated from the ColdFire core or the debug module.5.4.4 ResetA hardware reset clears the CACR disabling the instruction cache. The contents of the tag array are notaffected by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation bysetting CACR[24] before the cache can be enabled.5.4.5 Cache Miss Fetch Algorithm/Line FillsAs detailed in Section 5.1, “Instruction Cache Features,” the instruction cache hardware includes a 16-byteline fill buffer for providing temporary storage for the last fetched instruction.With the cache enabled as defined by CACR[31], a cacheable instruction fetch that misses in both the tagmemory and the line-fill buffer generates a external fetch. The size of the external fetch is determined by
