Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 24-79The iTD and siTD data structures each describe 8 micro-frames worth of transactions. The host controlleris allowed to cache one (or more) of these data structures in order to reduce memory traffic. There are threebasic caching models that account for the fact the isochronous data structures span 8 micro-frames. Thethree caching models are: no caching, micro-frame caching and frame caching.When the software is adding new isochronous transactions to the schedule, it always performs a read ofthe FRINDEX register to determine the current frame and micro-frame the host controller is currentlyexecuting. Of course, there is no information about where in the micro-frame the host controller is, so aconstant uncertainty factor of one micro-frame has to be assumed. Combining the knowledge of where thehost controller is executing with the knowledge of the caching model allows the definition of simplealgorithms for how closely the software can reliably work to the executing host controller.No caching is indicated with a value of zero in the Isochronous Scheduling Threshold field. The hostcontroller may pre-fetch data structures during a periodic schedule traversal (per micro-frame) but willalways dump any accumulated schedule state at the end of the micro-frame. At the appropriate timerelative to the beginning of every micro-frame, the host controller always begins schedule traversal fromthe frame list. The software can use the value of the FRINDEX register (plus the constant 1uncertainty-factor) to determine the approximate position of the executing host controller. When nocaching is selected, the software can add an isochronous transaction as near as 2 micro-frames in front ofthe current executing position of the host controller.Frame caching is indicated with a non-zero value in bit [7] of the Isochronous Scheduling Threshold field.In the frame-caching model, the system software assumes that the host controller caches one (or more)isochronous data structures for an entire frame (8 micro-frames). The software uses the value of theFRINDEX register (plus the constant 1 uncertainty) to determine the current micro-frame/frame (assumemodulo 8 arithmetic in adding the constant 1 to the micro-frame number). For any current frame N, if thecurrent micro-frame is 0 to 6, then the software can safely add isochronous transactions to Frame N + 1.If the current micro-frame is 7, then software can add isochronous transactions to Frame N + 2.Micro-frame caching is indicated with a non-zero value in the least-significant 3 bits of the IsochronousScheduling Threshold field. The system software assumes the host controller caches one or more periodicdata structures for the number of micro-frames indicated in the Isochronous Scheduling Threshold field.For example, if the count value were 2, then the host controller keeps a window of 2 micro-frames worthof state (current micro-frame, plus the next) on-chip. On each micro-frame boundary, the host controllerreleases the current micro-frame state and begins accumulating the next micro-frame state.24.9.9 Asynchronous ScheduleThe Asynchronous schedule traversal is enabled or disabled via the Asynchronous Schedule Enable bit inthe USBCMD register. If the Asynchronous Schedule Enable bit is cleared, then the host controller simplydoes not try to access the asynchronous schedule via the ASYNCLISTADDR register. Likewise, if theAsynchronous Schedule Enable bit is set, the host controller does use the ASYNCLISTADDR register totraverse the asynchronous schedule. Modifications to the Asynchronous Schedule Enable bit are notnecessarily immediate. Rather the new value of the bit will only be taken into consideration the next timethe host controller needs to use the value of the ASYNCLISTADDR register to get the next queue head.The Asynchronous Schedule Status bit in the USBSTS register indicates status of the asynchronousschedule. The system software enables (or disables) the asynchronous schedule by writing a one (or zero)
