IEEE 1149.1 Test Access Port (JTAG)MCF5253 Reference Manual, Rev. 121-6 Freescale Semiconductor21.5 JTAG Register Definitions21.5.1 JTAG Instruction Shift RegisterThe MCF5253 IEEE 1149.1A Standard implementation uses a 4-bit instruction-shift register withoutparity. This register transfers its value to a parallel hold register and applies one of eight possibleinstructions on the falling edge of TCK when the TAP state machine is in the update-IR state. To load theinstructions into the shift portion of the register, place the serial data on the TDI pin prior to each risingedge of TCK.Table 21-2 lists the public, usable instructions that are supported along with their encoding.The IEEE 1149.1A Standard requires the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions.IDCODE, CLAMP, HIGHZ are optional standard instructions that the MCF5253 implementation supportsand are described in the IEEE Standard 1149.1A. The RINGOSC and ORGATE are user definedinstructions only used for device test during manufacturing.21.5.1.1 EXTEST InstructionThe external test instruction (EXTEST) selects the boundary-scan register. The EXTEST instructionforces all output pins and bidirectional pins configured as outputs to the preloaded fixed values (with theSAMPLE/PRELOAD instruction) and held in the boundary-scan update registers. The EXTESTinstruction can also configure the direction of bidirectional pins and establish high-impedance states onsome pins. The EXTEST instruction becomes active on the falling edge of TCK in the update-IR statewhen the data held in the instruction-shift register is equivalent to hex 0.21.5.1.2 IDCODEThe IDCODE instruction selects the 32-bit IDcode register for connection as a shift path between the TDIpin and the TDO pin. This instruction lets users interrogate the MCF5253 to determine its version numberTable 21-2. JTAG InstructionsInstruction ABBR Class IR[3:0] Instruction SummaryEXTEST EXT Required 0000 Select BS register while applying fixed values to output pins and asserting functionalresetIDCODE IDC Optional 0001 Selects IDCODE register for shiftSAMPLE/PRELOADSMP Required 0010 Selects BS register for shift, sample, and preload without disturbing functionaloperationCLAMP CMP Optional 0011 Selects bypass while applying fixed values to output pins and asserting functionalresetHIGHZ HI_Z Optional 0100 Selects the bypass register while tri-stating all output pins and asserting functionalresetRINGOSC RING Optional 0111 User defined function for device testORGATE OR Optional 1000 User defined function for device testBYPASS BYP Required 1111 Selects the bypass register for data operations
