MCF5253 IntroductionMCF5253 Reference Manual, Rev. 11-8 Freescale Semiconductor1.5.4 Instruction CacheThe instruction cache improves system performance by providing cached instructions to the execution unitin a single clock cycle. The MCF5253 processor uses an 8K-byte, direct-mapped instruction cache toachieve 125 MIPS at 140 MHz. The cache is accessed by physical addresses, where each 16-byte lineconsists of an address tag and a valid bit. The instruction cache also includes a bursting interface for 16-bitand 8-bit port sizes to quickly fill cache lines.1.5.5 Internal 128-Kbyte SRAMThe 128-Kbyte on-chip SRAM is split over two banks, SRAM0 (64K) and SRAM1 (64K). It providessingle clock-cycle access for the ColdFire core. This SRAM can store processor stack and critical code ordata segments to maximize performance. Memory in the second bank (SRAM1) can be accessed underDMA.1.5.6 DRAM ControllerThe MCF5253 DRAM controller provides a glueless interface for one bank of DRAM, and can address upto 32MB. The controller supports a 16-bit data bus. The controller operates in page mode, non-page mode,and burst-page mode and supports SDRAMs.1.5.7 System InterfaceThe MCF5253 provides a glueless interface to 16-bit port size SRAM, ROM, and peripheral devices withindependent programmable control of the assertion and negation of chip-select and write-enable signals.The MCF5253 also supports bursting ROMs.1.5.8 External Bus InterfaceThe bus interface controller transfers data between the ColdFire core or DMA and memory, peripherals,or other devices on the external bus. The external bus interface provides 23 address lines, a 16-bit data bus,Output Enable, and Read/Write signals. This interface implements an extended synchronous protocol thatsupports bursting operations.1.5.9 USB 2.0 High-Speed On-The-GoThe USB module in the MCF5253 is used for communication to a PC or communication to slave devices,e.g. to download data from a hard disc player to a flash player, to a photo printer and so on. The USBsupports full Host mode functionality. The USB supports the OTG supplement to the USB 2.0specification. It operates as high speed, full speed and low speed host, and as high speed and full speeddevice. Host negotiation protocol (HNP) and session request protocol (SRP) are implemented withsoftware support.A USB 2.0 high-speed compatible PHY is integrated on-chip.
