System Integration Module (SIM)MCF5253 Reference Manual, Rev. 19-20 Freescale SemiconductorNOTEIf the SWP and SWT bits are modified to select a new software timeout,users must peform the software service sequence ($55 followed by $AAwritten to the SWSR) before the new timeout period takes effect.9.5.2.2 Software Watchdog Interrupt Vector RegisterThe SWIVR contains the 8-bit interrupt vector the SIM returns during an interrupt- acknowledge cycle inresponse to a SWT-generated interrupt. The following register illustrates the SWIVR programming model.The SWIVR is an 8-bit supervisor write-only register. This register is set to the uninitialized vector $0F atsystem reset.4–3SWTThe Software Watchdog Timing Delay bits (along with the SWP bit) select the timeout period for the SWT as shownin Table 9-19 . At system reset, the software watchdog timer is set to the minimum timeout period.2SWTASoftware Watchdog Transfer Acknowledge Enable0 SWTA Transfer Acknowledge disabled.1 SWTA Assert Transfer Acknowledge enabled.After 1 SWT timeout period of the unacknowledged assertion of the SWT interrupt, the Software Watchdog TransferAcknowledge will assert, which allows SWT to terminate a bus cycle and allow the IACK to occur.1SWTAVALSoftware Watchdog Transfer Acknowledge Valid0 SWTA Transfer Acknowledge has NOT occurred.1 SWTA Transfer Acknowledge has occurred. Write a 1 to clear this flag bit.0 Reserved, should be cleared.Table 9-19. SWT Timeout PeriodSWP SWT[1:0] SWT TIMEOUT PERIOD0 00 29 / BCLK0 01 211 / BCLK0 10 213 / BCLK0 11 215 / BCLK1 00 222 / BCLK1 01 224 / BCLK1 10 226 / BCLK1 11 228 / BCLKTable 9-18. System Protection Control Register (SYPCR) Field Descriptions (continued)Field Description
