Analog to Digital Converter (ADC)MCF5253 Reference Manual, Rev. 112-4 Freescale Semiconductor12.4 Functional DescriptionEach ADC input channel has its own on-chip comparator the output of which is multiplexed with thedigital section.The reason to have separate comparators for each channel allows for the inputs to be usedas GPI’s. In this mode the ADREF should be a fixed level (typically VDD/2) and each comparator is thenbeing used to indicate if its input is above or below this reference (HIGH or LOW). The state of each GPIin this case is read using the GPIO_READ registers.NOTEIt is possible to mix the use of each of these inputs between ADC and GPIfunction as the ADOUT/SCLK4/GPIO58 pin can be switched betweenproviding the ramping ADOUT signal (ADC mode) to providing a fixedlevel (VDD/2) by switching its operation to SCLK4 mode whenappropriate. SCLK4 will output a 50% duty cycle clock. Which whenintegrated will produce a reference voltage close to VDD/2. The outputfrequency of SCLK4 can be varied by programming the IIS4 Audio register.See Section 17.5, “Serial Audio Interface (I2S/EIAJ) RegisterDescriptions.”The ADC uses the sigma-delta modulation principle. The ADC external components required are anintegrator circuit comprising of a resistor and capacitor. The desired values for this integrator network aredependent on the BUSCLK clock frequency and the associated setting of the ADconfig[ADCLK_SEL]bits, which determine the maximum ADOUT PWM frequency.12.4.1 Recommendations to Set-up of ADC and External ComponentsDo not run the ADC clock any faster than 10 MHz. This results in a maximum sampling frequency of2441 Hz (10 MHz/4096).To calculate the external component values use the following equation:Eqn. 12-1where K is a constant. If K is small, the ripple on the comparator input will be quite large, and there willbe some mis-measurement because the average value on both comparator pins is not equal. If K is small,Table 12-3. ADvalue Register Field DescriptionsField Description15–13 Reserved, should be cleared.12OFOverflow. Indicates the input voltage is out of range. The ADC block does not support full rail-to-railconversions.0 No overflow condition.1 Overflow. Input signal is outside the operating voltage range of the ADC.11–0ADVALUEAD measurement result.RC K t×=
